A survey on fault-tolerant application mapping techniques for network-on-chip
N Kadri, M Koudil - Journal of Systems Architecture, 2019 - Elsevier
Reliability is becoming a major concern in Networks-on-Chips (NoCs) design. Several
techniques have been proposed in the literature to deal with different types of faults at …
techniques have been proposed in the literature to deal with different types of faults at …
Problems and challenges of emerging technology networks− on− chip: A review
AB Achballah, SB Othman, SB Saoud - Microprocessors and Microsystems, 2017 - Elsevier
Abstract Networks− on− chip (NoC) are an alternative to alleviate the problems of legacy
interconnect fabrics. However, many emerging technology NoC are developed and are now …
interconnect fabrics. However, many emerging technology NoC are developed and are now …
Fault-tolerant topology generation method for application-specific network-on-chips
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor
densities on chips dramatically increase. While nanometer feature sizes allow denser chip …
densities on chips dramatically increase. While nanometer feature sizes allow denser chip …
Fault-tolerant application-specific topology-based NoC and its prototype on an FPGA
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for
meeting current application requirements. Interconnection links are the primary components …
meeting current application requirements. Interconnection links are the primary components …
True crosstalk aware incremental placement with noise map
Crosstalk noise has become an important issue as technology scales down for timing and
signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or …
signal integrity closure. Existing works to fix crosstalk noise are mostly done at the routing or …
Network topology transformation for fault tolerance in spacewire onboard networks
I Lavrovskaya, V Olenev - 2018 22nd Conference of Open …, 2018 - ieeexplore.ieee.org
The paper presents a network transformation algorithm for fault tolerance in SpaceWire
onboard networks which is implemented in SANDS computer-aided design system. We give …
onboard networks which is implemented in SANDS computer-aided design system. We give …
FPGA implementation of a fault-tolerant application-specific NoC design
Today's integrated circuits are more susceptible to permanent link failures than before as a
result of diminishing technology sizes. Even a single link failure can make an entire chip …
result of diminishing technology sizes. Even a single link failure can make an entire chip …
Design space exploration using utnocs and genetic algorithm
JW De Mesquita, MO da Cruz… - 2016 VI Brazilian …, 2016 - ieeexplore.ieee.org
During the design of multiprocessor architectures, the design space exploration step may be
aided by tools that assist and accelerate this process. The project of architectures whose …
aided by tools that assist and accelerate this process. The project of architectures whose …
Fault-tolerant routing for irregular-topology-based network-on-chips
VB Ajabshir, S Tosun - 2014 Second International Symposium …, 2014 - ieeexplore.ieee.org
The designers favor irregular topologies for Network-on-Chip (NoC) architectures due to
their lower energy consumptions, lower latencies, and higher throughputs than their regular …
their lower energy consumptions, lower latencies, and higher throughputs than their regular …
Трансформация сети для повышения отказоустойчивости в бортовых сетях SpaceWire
ИЯ Лавровская, ВЛ Оленев - Научная сессия ГУАП, 2018 - elibrary.ru
Статья представляет алгоритм трансформации сети для бортовых сетей SpaceWire.
Данный алгоритм реализован в системе автоматизированного проектирования …
Данный алгоритм реализован в системе автоматизированного проектирования …