Programming the behavior of individual chips or strata in a 3D stack of integrated circuits
LT Pang, JA Silberman, MR Wordeman - US Patent 8,928,350, 2015 - Google Patents
There is provided a strata manager Within a 3D chip stack having two or more strata. The
strata manager includes a plurality of scannable con? guration registers, each being …
strata manager includes a plurality of scannable con? guration registers, each being …
Method and apparatus for 3D IC test
SA Chi - US Patent 9,164,147, 2015 - Google Patents
An apparatus comprises a die comprising a plurality of switch/router circuits; and a plurality
of additional dies. Each respective one of the plurality of additional dies comprises: a …
of additional dies. Each respective one of the plurality of additional dies comprises: a …
Disposable built-in self-test devices, systems and methods for testing three dimensional integrated circuits
KA Jenkins, S Kim - US Patent 7,863,918, 2011 - Google Patents
A device and method for self-testing an integrated circuit layer for a three-dimensional
integrated circuit includes integrally forming a disposable self-test circuit on a common …
integrated circuit includes integrally forming a disposable self-test circuit on a common …
3D chip stack skew reduction with resonant clock and inductive coupling
JJ Kim, YS Lin, LT Pang, JA Silberman - US Patent 8,576,000, 2013 - Google Patents
US8576000B2 - 3D chip stack skew reduction with resonant clock and inductive coupling -
Google Patents US8576000B2 - 3D chip stack skew reduction with resonant clock and inductive …
Google Patents US8576000B2 - 3D chip stack skew reduction with resonant clock and inductive …
Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network
TJ Bucelot, LT Pang, PJ Restle - US Patent 8,525,569, 2013 - Google Patents
US PATENT DOCUMENTS 4,868,712 A 9, 1989 Woodman 5,200,631 A 4, 1993 Austin et al.
5,280,184 A 1/1994 Jokerst et al. 5,655,290 A 8, 1997 Moresco et al. 5,702.984 A 12/1997 …
5,280,184 A 1/1994 Jokerst et al. 5,655,290 A 8, 1997 Moresco et al. 5,702.984 A 12/1997 …
Implementing fault tolerance in computer system memory
S Li - US Patent 10,078,567, 2018 - Google Patents
A method of implementing fault tolerance in computer memory includes translating a logical
address to a first physical address for a first memory location in the computer memory. The …
address to a first physical address for a first memory location in the computer memory. The …
Vertical power budgeting and shifting for three-dimensional integration
P Bose, GD Carpenter, MS Floyd, E Kursun… - US Patent …, 2013 - Google Patents
US 2013/OO55185A1 Feb. 28, 2013 A method is provided for managing power distribution
on a (51) Int. Cl. three-dimensional chip stack having two or more strata, a G06F …
on a (51) Int. Cl. three-dimensional chip stack having two or more strata, a G06F …
3D chip stack skew reduction with resonant clock and inductive coupling
JJ Kim, YS Lin, LT Pang, JA Silberman - US Patent 8,466,739, 2013 - Google Patents
(*) Notice: Subject to any disclaimer, the term of this(Continued) patent is extended or
adjusted under 35 USC 154 (b) by 0 days. OTHER PUBLICATIONS (21) Appl. No …
adjusted under 35 USC 154 (b) by 0 days. OTHER PUBLICATIONS (21) Appl. No …
AC supply noise reduction in a 3D stack with voltage sensing and clock shifting
JJ Kim, YS Lin, LT Pang, JA Silberman - US Patent 8,587,357, 2013 - Google Patents
4,868,712 A 9, 1989 Woodman 5,200,631 A 4, 1993 Austin et al. 5,280,184 A 1/1994 Jokerst
et al. 5,655,290 A 8, 1997 Moresco et al. 5,702.984 A 12/1997 Bertin et al. some of the …
et al. 5,655,290 A 8, 1997 Moresco et al. 5,702.984 A 12/1997 Bertin et al. some of the …
Input output for an integrated circuit
CM Fu - US Patent 9,773,754, 2017 - Google Patents
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5/2013 Lin et al. 8, 610, 488 B2 12/2013 Yu et al. 8, 625, 240 B2 1/2014 Chung et al. 8, 631 …