Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

V Herdt, R Drechsler - Science China Information Sciences, 2022 - Springer
Virtual prototypes (VPs) are crucial in today's design flow. VPs are predominantly created in
SystemC transaction-level modeling (TLM) and are leveraged for early software …

[图书][B] Enhanced Virtual Prototyping

RDV Herdt, D Große, R Drechsler - 2021 - Springer
Virtual Prototypes (VPs) play a very important role to cope with the rising complexity in the
design flow of embedded devices. A VP is essentially an executable abstract model of the …

Formal techniques for effective co-verification of hardware/software co-designs

R Mukherjee, M Purandare, R Polig… - Proceedings of the 54th …, 2017 - dl.acm.org
Verification is indispensable for building reliable of hardware/software co-designs. However,
the scope of formal methods in this domain is limited. This is attributed to the lack of unified …

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware

BY Huang, S Ray, A Gupta, JM Fung… - Proceedings of the 55th …, 2018 - dl.acm.org
Formal security verification of firmware interacting with hardware in modern Systems-on-
Chip (SoCs) is a critical research problem. This faces the following challenges:(1) design …

Early concolic testing of embedded binaries with virtual prototypes: A RISC-V case study

V Herdt, D Große, HM Le, R Drechsler - Proceedings of the 56th Annual …, 2019 - dl.acm.org
Extensive testing of IoT SW is very important to prevent errors and security vulnerabilities. In
the SW domain the automated concolic testing technique has been shown very effective. In …

Template-based synthesis of instruction-level abstractions for SoC verification

P Subramanyan, Y Vizel, S Ray… - 2015 Formal Methods in …, 2015 - ieeexplore.ieee.org
Contemporary integrated circuits are complex system-on-chip (SoC) designs consisting of
programmable cores along with accelerators and peripherals controlled by firmware running …

Template-based parameterized synthesis of uniform instruction-level abstractions for SoC verification

P Subramanyan, BY Huang, Y Vizel… - … on Computer-Aided …, 2017 - ieeexplore.ieee.org
Modern system-on-chip (SoC) designs comprise programmable cores, application-specific
accelerators, and I/O devices. Accelerators are controlled by software/firmware and …

Verification of embedded binaries using coverage-guided fuzzing with systemc-based virtual prototypes

V Herdt, D Große, J Wloka, T Güneysu… - Proceedings of the 2020 …, 2020 - dl.acm.org
Extensive verification of embedded SW is very important to avoid errors and security
vulnerabilities. Therefore, mainly simulation-based methods are employed that leverage …

Formal verification of application and system programs based on a validated x86 ISA model

S Goel - 2016 - repositories.lib.utexas.edu
Two main kinds of tools available for formal software verification are point tools and general-
purpose tools. Point tools are targeted towards bug-hunting or proving a fixed set of …

Generating architecture-level abstractions from RTL designs for processors and accelerators part i: Determining architectural state variables

Y Zeng, BY Huang, H Zhang, A Gupta… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Today's Systems-on-Chips (SoCs) comprise general/special purpose programmable
processors and specialized hardware modules referred to as accelerators. These …