We propose a power-driven flip-flop merging and relocation approach that can be applied
after conventional timing-driven placement and before clock network synthesis. It targets to …

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a
single-phase clock, employing topological and adaptive coupling methods. The proposed …

This paper enumerates a low power, high speed design of flip-flop having less number of
transistors. In flip-flop design only one transistor is being clocked by short pulse train which …

A novel master-slave flip-flop is designed using 18 transistors by topological techniques.
The proposed flip-flop circuit (PFC) is compared with the existing flip-flops. Key parameters …

In this paper, a design of low power m-sequence code generator is proposed. The efficiency
of producing the code sequence within the region of sub-threshold voltage is investigated …

In integrated circuits, power consumption is a one of the top three challenges like area,
power and speed. Power optimization of IC's can be achieved in gate level, logical level …

This paper enumerates the efficient design and analysis of low power CNTFET True single
phase clock logic D Flip flop based shift registers. The TSPC D flip flop and shift registers are …

Power dissipation in the modern integrated circuits (IC) is an important parameter to
determine the performance inside a chip manufactured using ≦ 65 nm process technology …

A Conditional Feedthrough Pulsed Flip-Flop Using MTCMOS technique is proposed in this
paper. Power and delay are optimized in this paper compared to the existing model with the …

This paper enumerates the design of low power and high speed double edge triggered True
Single Phase Clocking (TSPC) D-flip-flop. The TSPC CMOS flip-flop uses only one clock …