Software engineers now face the difficult task of refactoring serial programs for parallel
execution on multicore processors. Currently, they are offered little guidance as to how much …

Dennard scaling has come to an end. General-purpose architecture now can hardly have
major improvements in power efficiency. Therefore, recently researchers have been actively …

Hardware accelerators are an active field of research in computer architecture as one
solution to overcome hurdles such as dark silicon. A host processor interfaces with an …

Recent developments in architecture research warrant the need for efficient host cores to
interact and manage multiple accelerators in a system-on-chip design. Existing designs …

Traditionally, computer architecture has been dominated by overly complex instruction sets
that created a” solution” to every problem by adding another instruction. If these complex …

As processor design complexities increase, so do their verification complexities. As a
consequence, processor verification has slowed down and become less reliable. The recent …

This thesis presents the RTL implementation and evaluation of a non-blocking L2 victim
cache for the open-source HammerBlade manycore architecture. The primary objective of …

The Reduced Instruction Set Computer (RISC)-V architecture, celebrated for its open-source
flexibility and modular design, is a cornerstone for modern computing innova-tions …

As processor design complexities increase, so do their verification complexities. As a
consequence, processor verification has slowed down and become less reliable. The recent …

Parallelization of an existing sequential application to achieve a good speed-up on a data-
parallel infrastructure is quite difficult and time consuming effort. One of the important steps …