A systematic review of hardware-accelerated compression of remotely sensed hyperspectral images

A Altamimi, B Ben Youssef - Sensors, 2021 - mdpi.com
Hyperspectral imaging is an indispensable technology for many remote sensing
applications, yet expensive in terms of computing resources. It requires significant …

FPGA–accelerated CNN for real-time plant disease identification

Y Luo, X Cai, J Qi, D Guo, W Che - Computers and Electronics in …, 2023 - Elsevier
Using convolutional neural network (CNN) to identify plant diseases in-situ is a hot research
topic in smart agriculture. Due to the memory-intensive and compute-intensive …

Debugging in the brave new world of reconfigurable hardware

J Ma, G Zuo, K Loughlin, H Zhang, A Quinn… - Proceedings of the 27th …, 2022 - dl.acm.org
Software and hardware development cycles have traditionally been quite distinct. Software
allows post-deployment patches, which leads to a rapid development cycle. In contrast …

A comparative analysis of HDL and HLS for developing CNN accelerators

S Srilakshmi, GL Madhumati - 2023 Third International …, 2023 - ieeexplore.ieee.org
In today's world, complexity is increasing and market demands new development tools for
Field Programmable Gate array (FPGA) in Convolution Neural Networks (CNN) applications …

[HTML][HTML] Development of a resource-efficient FPGA-based neural network regression model for the ATLAS muon trigger upgrades

R Ospanov, C Feng, W Dong, W Feng, K Zhang… - The European Physical …, 2022 - Springer
This paper reports on the development of a resource-efficient FPGA-based neural network
regression model for potential applications in the future hardware muon trigger system of the …

Quantized CNN-based efficient hardware architecture for real-time hand gesture recognition

M Jaiswal, V Sharma, A Sharma, S Saini… - Microelectronics Journal, 2024 - Elsevier
Abstract Nowadays, Convolutional Neural Networks (CNN) have been widely adopted for
vision-based hand gesture recognition. Several existing CNN architectures designed for …

Hardware Design of Lightweight Binary Classification Algorithms for Small-Size Images on FPGA

S Saglam, S Bayar - IEEE Access, 2024 - ieeexplore.ieee.org
This study explores the implementation of lightweight binary classification algorithms on low-
cost Field-Programmable Gate Arrays (FPGAs) for medical image analysis. Recognizing the …

Model-Based FPGA Implementation of a 6-DoF Dynamical Model Accelerator

S Memis, R Yeniceri - IEEE Access, 2024 - ieeexplore.ieee.org
The mathematical model of 6-DoF dynamics is used in different applications. In general,
software-based solutions are utilized to implement the 6-DoF dynamic model. This paper …

Accelerating LSTM-based High-Rate Dynamic System Models

E Kabir, D Coble, JN Satme… - … Conference on Field …, 2023 - ieeexplore.ieee.org
In this paper, we evaluate the use of a trained Long Short-Term Memory (LSTM) network as
a surrogate for a Euler-Bernoulli beam model, and then we describe and characterize an …

Model based design of FMCW radar processing systems on FPGA platforms

H Almorin, B Le Gal, C Jego… - 2023 26th Euromicro …, 2023 - ieeexplore.ieee.org
The use of high level synthesis (HLS) tools is progressing in the industrial and academic
worlds as they have gained in maturity. In the last few years, they are commonly applied to …