Design of hybrid sorting unit

VS Harshini, KKS Kumar - 2019 International Conference on …, 2019 - ieeexplore.ieee.org
Sorting is the fundamental function of any process for most of the application, The widely
used hardware sorting algorithm in VLSI are Bitonic merge sort and Bitonic odd even sort …

Novel MIMO detection algorithm for high-order constellations in the complex domain

M Mahdavi, M Shabany - IEEE transactions on very large scale …, 2012 - ieeexplore.ieee.org
A novel detection algorithm with an efficient VLSI architecture featuring efficient operation
over infinite complex lattices is proposed. The proposed design results in the highest …

An area-efficient message passing detector for massive MIMO systems

S Song, Z Wang - IEEE Transactions on Circuits and Systems I …, 2021 - ieeexplore.ieee.org
Recently, massive multiple-input multiple-output (MIMO) detection schemes based on
message passing detection (MPD) have attracted extensive attention due to their good …

Achieving near MAP performance with an excited Markov chain Monte Carlo MIMO detector

JC Hedstrom, CH Yuen, RR Chen… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
We introduce a revised derivation of the bitwise Markov Chain Monte Carlo (MCMC) multiple-
input multipleoutput (MIMO) detector. The new approach resolves the previously reported …

Hardware design of low-power high-throughput sorting unit

SH Lin, PY Chen, YN Lin - IEEE Transactions on Computers, 2017 - ieeexplore.ieee.org
Sorting is one of the most fundamental topics in computer science. Since partial sorting with
lower costs would be much more feasible than the complete sorting method for some …

Efficient design of magnitude and 2's complement comparators

F Ntouskas, C Efstathiou, K Pekmestzi - Integration, 2020 - Elsevier
Digital comparators are important arithmetic components used in digital systems to
determine if two numbers are equal, or if one number is greater or less than the other. In this …

Efficient low-latency implementation of CORDIC-based sorted QR decomposition for multi-Gbps MIMO systems

H Lee, K Oh, M Cho, Y Jang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This brief presents the efficient VLSI implementation of coordinate rotation digital computer
(CORDIC)-based sorted QR decomposition (SQRD) for multiple-input and multiple-output …

Design and implementation of flexible dual-mode soft-output MIMO detector with channel preprocessing

Z Yan, G He, Y Ren, W He, J Jiang… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This paper proposes a flexible dual-mode soft-output multiple-input multiple-output (MIMO)
detector to support open-loop and closed-loop in Chinese enhanced ultra high throughput …

A 3.1 Gb/s 8 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition

CF Liao, JY Wang, YH Huang - IEEE Transactions on Very …, 2014 - ieeexplore.ieee.org
This paper presents the VLSI implementation of a lattice-reduction-aided (LRA) detection
system. The proposed system includes a QR decomposition, lattice reduction (LR) …

VLSI implementation of a fully-pipelined K-best MIMO detector with successive interference cancellation

IA Bello, B Halak, M El-Hajjar, M Zwolinski - Circuits, Systems, and Signal …, 2019 - Springer
Multiple-input multiple-output (MIMO) technology is envisaged to play an important role in
future wireless communications. To this end, novel algorithms and architectures are required …