Ultra-low latency mobile networking
Mobile networking to achieve the ultra-low latency goal of 1 msec enables massive
operation of autonomous vehicles and other intelligent mobile machines, and emerges as …
operation of autonomous vehicles and other intelligent mobile machines, and emerges as …
A low-power scalable signal processing chip platform for 5G and beyond-kachel
G Fettweis, M Hassler, R Wittig, E Matus… - 2019 53rd Asilomar …, 2019 - ieeexplore.ieee.org
Current 5G chip solutions have the focus on delivering the extreme: an end-to-end
experience of 5ms latency and a minimum of 1Gb/s data rate. This is what seems to be the …
experience of 5ms latency and a minimum of 1Gb/s data rate. This is what seems to be the …
Memory-efficient deep learning on a SpiNNaker 2 prototype
The memory requirement of deep learning algorithms is considered incompatible with the
memory restriction of energy-efficient hardware. A low memory footprint can be achieved by …
memory restriction of energy-efficient hardware. A low memory footprint can be achieved by …
Efficient reward-based structural plasticity on a SpiNNaker 2 prototype
Advances in neuroscience uncover the mechanisms employed by the brain to efficiently
solve complex learning tasks with very limited resources. However, the efficiency is often lost …
solve complex learning tasks with very limited resources. However, the efficiency is often lost …
Agiler: An adaptive heterogeneous tile-based many-core architecture for risc-v processors
A Kamaleldin, D Göhringer - IEEE Access, 2022 - ieeexplore.ieee.org
Tile-based many-core architectures are extensively used in modern system-on-chip designs
to achieve scalable computing performance with adequate energy efficiency. Heterogeneity …
to achieve scalable computing performance with adequate energy efficiency. Heterogeneity …
A hardware/software stack for heterogeneous systems
J Castrillon, M Lieber, S Klüppelholz… - … on Multi-Scale …, 2017 - ieeexplore.ieee.org
Plenty of novel emerging technologies are being proposed and evaluated today, mostly at
the device and circuit levels. It is unclear what the impact of different new technologies at the …
the device and circuit levels. It is unclear what the impact of different new technologies at the …
Towards a modular RISC-V based many-core architecture for FPGA accelerators
Multi-/Many-core architectures are emerging as scalable, high-performance and energy-
efficient computing platforms suitable for a variety of application domains from edge to cloud …
efficient computing platforms suitable for a variety of application domains from edge to cloud …
Dynamic power management for neuromorphic many-core systems
This paper presents a dynamic power management architecture for neuromorphic many-
core systems, such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) …
core systems, such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) …
Access interval prediction by partial matching for tightly coupled memory systems
V Razilov, R Wittig, E Matúš, G Fettweis - International Journal of Parallel …, 2024 - Springer
In embedded systems, tightly coupled memories (TCMs) are usually shared between
multiple masters for the purpose of hardware efficiency and software flexibility. On the one …
multiple masters for the purpose of hardware efficiency and software flexibility. On the one …
{M³x}: Autonomous Accelerators via {Context-Enabled}{Fast-Path} Communication
Performance and efficiency requirements are driving a trend towards specialized
accelerators in both datacenters and embedded devices. In order to cut down …
accelerators in both datacenters and embedded devices. In order to cut down …