Recent years have seen a dramatic increase in the microarchitectural complexity of
processors. This increase in complexity presents a twofold challenge for the field of …

The unabating growth of the memory needs of emerging datacenter applications has
exacerbated the scalability bottleneck of virtual memory. However, reducing the excessive …

Online Reinforcement Learning (RL) has been adopted as an effective mechanism in
various decision-making problems in microarchitecture. Its high adaptability and the ability to …

Multi-GPU systems have emerged as a desirable platform to deliver high computing
capabilities and large memory capacity to accommodate large dataset sizes. However …

Address translation is a performance bottleneck in data-intensive workloads due to large
datasets and irregular access patterns that lead to frequent high-latency page table walks …

The effort to reduce address translation overheads has typically targeted data accesses
since they constitute the overwhelming portion of the second-level TLB (STLB) misses in …

To support highly scalable and fine-grained computing paradigms such as microservices
and serverless computing better, modern hardware-assisted confidential computing …

The increase in working set sizes of contemporary applications outpaces the growth in
cache sizes, resulting in frequent main memory accesses that deteriorate system …

To alleviate the performance and energy overheads of contemporary applications with large
data footprints, we propose the Two Level Perceptron (TLP) predictor, a neural mechanism …

Multi-GPU systems have become a popular platform to meet the ever-growing application
demands. However, employing multiple GPUs does not guarantee proportional performance …