A method includes generating first frequency metrics for a first received network clock signal
using a local reference clock signal. The method includes, in response to the first received …

Techniques for generating a fail safe clock signal improves reliability of one or more output
clock signals generated based on one or more input clock signals and an internally …

MEMS resonators generate respective first and second clock signals and a locked-loop
reference clock generator gener ates a reference clock signal having a frequency that is …

An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-
N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and …

(57) ABSTRACT A system for assigning a characterization and calibrating a parameter is
disclosed. The system includes a frequency mea Surement circuit and a finite state machine …

Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked
loop. An offset signal can be applied to adjust an input signal provided to an integrator of a …

A method for operating a clock product includes generating a quality determination for a
reference clock signal based on frequency metrics for a plurality of independent clock …

A method for generating a clock signal includes selecting a primary reference clock signal or
a secondary reference clock signal as a reference clock signal for a phase-locked loop …

In a high resolution temperature sensor, first and second MEMS resonators generate
respective first and second clock signals and a locked-loop reference clock generator gener …

(57) ABSTRACT A light emitting diode (LED) backlight system and a driving apparatus and a
driving method thereof are provided. The driving apparatus is suitable for an LED backlight …