Clock data recovery circuitry associated with programmable logic device circuitry
E Aung, H Lui, P Butler, J Turner, R Patel… - US Patent …, 2007 - Google Patents
A programmable logic device (“PLD”) is augmented with programmable clock data recover
(“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR …
(“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR …
Clock data recovery circuitry associated with programmable logic device circuitry
E Aung, H Lui, P Butler, J Turner, R Patel… - US Patent …, 2008 - Google Patents
(57) ABSTRACT A programmable logic device (“PLD) is augmented with programmable
clock data recover (“CDR) circuitry to allow the PLD to communicate via any of a large …
clock data recover (“CDR) circuitry to allow the PLD to communicate via any of a large …
Method and apparatus for bit error rate detection
MH Perrott - US Patent 6,988,227, 2006 - Google Patents
(54) METHOD AND APPARATUS FOR BIT 6,347,128 B1 2/2002 Ransijn ERROR RATE
DETECTION 6,392.457 B1 5/2002 Ransijn 6,463,109 B1 10/2002 McCormacket al.(75) …
DETECTION 6,392.457 B1 5/2002 Ransijn 6,463,109 B1 10/2002 McCormacket al.(75) …
Method and apparatus for acquiring a frequency without a reference clock
M Perrott - US Patent 7,205,852, 2007 - Google Patents
(57) ABSTRACT A clock and data recovery system acquires a clock embed ded in an input
data stream by detecting the occurrence of transitions in the input data stream falling into a …
data stream by detecting the occurrence of transitions in the input data stream falling into a …
Clock data recovery circuitry associated with programmable logic device circuitry
E Aung, H Lui, P Butler, J Turner, R Patel… - US Patent …, 2010 - Google Patents
5,481,563 5483, 180 5,552,942 5,610,953 5,689,195 5,726.988 5,742,765 5,757,240
5,760,844 5,781,038 5,793,822 5,802,103 5,805,632 5,838,749 5,896,067 5,896,561 …
5,760,844 5,781,038 5,793,822 5,802,103 5,805,632 5,838,749 5,896,067 5,896,561 …
Detection of frequency differences between signals
G Gutierrez - US Patent 6,680,991, 2004 - Google Patents
A lock detector is described for detecting a difference between the frequencies of a first and
a second input signal. The lock detector includes first and second beat generators …
a second input signal. The lock detector includes first and second beat generators …
Robust false locking prevention in referenceless frequency acquisition
Z Fu, AB Eldredge - US Patent 7,375,591, 2008 - Google Patents
US7375591B2 - Robust false locking prevention in referenceless frequency acquisition -
Google Patents US7375591B2 - Robust false locking prevention in referenceless frequency …
Google Patents US7375591B2 - Robust false locking prevention in referenceless frequency …
An area-and power-efficient half-rate clock and data recovery circuit
This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved
architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared …
architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared …
5 Gb/s 2: 1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS
S Shi, Z Wang, C Zhang, P Miao, L Tang - Analog Integrated Circuits and …, 2012 - Springer
Abstract A 5 Gb/s 2: 1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC
0.18-μm CMOS process. A clock generation circuit (CGC) is also integrated to provide the …
0.18-μm CMOS process. A clock generation circuit (CGC) is also integrated to provide the …
A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS
Z Changchun, W Zhigong, S Si… - Journal of …, 2010 - iopscience.iop.org
Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang
phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in …
phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in …