20 years of turbo coding and energy-aware design guidelines for energy-constrained wireless applications
MF Brejza, L Li, RG Maunder… - … Surveys & Tutorials, 2015 - ieeexplore.ieee.org
During the last two decades, wireless communication has been revolutionized by near-
capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit …
capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit …
Security and vulnerability implications of 3D ICs
Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D
integration technology emerges as a viable option to improve chip performance and …
integration technology emerges as a viable option to improve chip performance and …
TSV-based 3-D ICs: Design methods and tools
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
Design for manufacturability and reliability for TSV-based 3D ICs
The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum
recently for industry adoption. However, as TSV involves disruptive manufacturing …
recently for industry adoption. However, as TSV involves disruptive manufacturing …
Physical design automation for 3D chip stacks: challenges and solutions
J Knechtel, J Lienig - Proceedings of the 2016 on International …, 2016 - dl.acm.org
The concept of 3D chip stacks has been advocated by both industry and academia for many
years, and hailed as one of the most promising approaches to meet ever-increasing …
years, and hailed as one of the most promising approaches to meet ever-increasing …
Effect of process variations in 3D global clock distribution networks
In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew
differs from 2D circuits. The combined effect of inter-die and intra-die process variations on …
differs from 2D circuits. The combined effect of inter-die and intra-die process variations on …
TSV-Cluster defect tolerance using tree-based redundancy for yield improvement of 3-D ICs
Through silicon via (TSV)-based 3-D integrated circuit (3-D IC) has several advantages like
high density, high bandwidth, and low-power consumption. However, many defects in TSV …
high density, high bandwidth, and low-power consumption. However, many defects in TSV …
Whitespace-aware TSV arrangement in 3-D clock tree synthesis
Through-silicon-via (TSV) could provide vertical connections among different dies in 3-D
integrated circuits (3-D ICs), but the significant silicon area occupied by TSVs may bring …
integrated circuits (3-D ICs), but the significant silicon area occupied by TSVs may bring …
TSV-aware topology generation for 3D clock tree synthesis
Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation
and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most …
and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most …
Resource allocation and design techniques of prebond testable 3-D clock tree
TY Kim, T Kim - IEEE Transactions on Computer-Aided Design …, 2012 - ieeexplore.ieee.org
In 3-D stacked integrated circuit (IC) manufacturing, for the acceptable high yield, it is
essential to stack only known good dies by testing the individual dies at the prebond stage …
essential to stack only known good dies by testing the individual dies at the prebond stage …