Floorplanning for optimizing area using sequence pair and hybrid optimization
P Tamarana, AK Kumari - Multimedia Tools and Applications, 2024 - Springer
Physical design is major key processes in integrating the circuit into the chip area in VLSI
circuit design. A netlist is accepted as input by a floorplanning stage, provided by the …
circuit design. A netlist is accepted as input by a floorplanning stage, provided by the …
FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path …
Abstract Optimized Field Programmable Gate Array (FPGA) implementation of Cellular
Automata (CA) for high speed design requires knowledge of the platform specific logic cell …
Automata (CA) for high speed design requires knowledge of the platform specific logic cell …
AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design
Y Li, Y Zhang, J Liu, J Gong, J Wang, J Lai, X Tao… - Integration, 2022 - Elsevier
For FPGA circuit design, exploring the FPGA design space for the optimal performance
becomes important and also challenging. The popular tool COFFE was built on an academic …
becomes important and also challenging. The popular tool COFFE was built on an academic …
Implementation of Multi Bit Error Detection and Correction using Low Density Parity Check Codes
B Suman, MJC Prasad - 2022 1st IEEE International …, 2022 - ieeexplore.ieee.org
Data transmission in advanced space communications are suffering with the different types
of noises. Further, these noises cause burst errors in data. Thus, the low-density parity …
of noises. Further, these noises cause burst errors in data. Thus, the low-density parity …
[PDF][PDF] Partial Pseudo-Random Hashing for Transactional Memory Read/Write Data Processing and Validation
GM Sridevi, A DV, BV Prakash - Karbala International Journal of Modern …, 2022 - iasj.net
Abstract Development of a bypass parallel processing block is one of the emerging and
interesting research areas in memory read/write application domain. Many Random Number …
interesting research areas in memory read/write application domain. Many Random Number …
Generation and Implementation of Random Number Architecture using Difference Expansion for Digital Circuits
SN Devi, S Sasipriya - 2022 Third International Conference on …, 2022 - ieeexplore.ieee.org
Unified logic and very large-scale integration (VLSI) circuitry have been created to generate
random numbers from various distributions such as uniform, exponential, and Gauss …
random numbers from various distributions such as uniform, exponential, and Gauss …
VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications
S Poongodi, AS Rani - Ratio Mathematica, 2022 - search.proquest.com
Data transmission in advanced space communications are suffering with the different types
of noises. Further, these noises causeburst errors indata. Thus, the error correction codes …
of noises. Further, these noises causeburst errors indata. Thus, the error correction codes …
[PDF][PDF] Convolutional Encoder-Based Error Detection and Correction Techniques for Enhanced Reliability in 5G Communication Systems
K Shirisha, M Rajkumar, B Teja, A Himavarshini… - ijarst.in
The advent of 5G communication systems has ushered in a new era of connectivity,
promising unprecedented data speeds and low-latency communication. However, the …
promising unprecedented data speeds and low-latency communication. However, the …