Potential benefits and sensitivity analysis of dopingless transistor for low power applications
In this paper, we report the potential benefits of dopingless double-gate field-effect transistor
(DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The …
(DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The …
Ultra low power junctionless MOSFETs for subthreshold logic applications
MS Parihar, D Ghosh, A Kranti - IEEE Transactions on Electron …, 2013 - ieeexplore.ieee.org
In this paper, we report the potential of junctionless (JL) MOS transistors for ultra low power
(ULP) subthreshold logic applications. It is demonstrated that double gate (DG) JL devices …
(ULP) subthreshold logic applications. It is demonstrated that double gate (DG) JL devices …
Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor
This paper proposes a simplified analytical approach to analyze the influence of process
variations including quantum confinement effect (QCE) on the functionality of ultralow power …
variations including quantum confinement effect (QCE) on the functionality of ultralow power …
Error reduction of SRAM-based physically unclonable function for chip authentication
SRAM-based physically unclonable function (PUF) is an attractive security primitive for
cryptographic protocol and security architecture because SRAM itself is one of the most …
cryptographic protocol and security architecture because SRAM itself is one of the most …
Enhancing performance of dual-gate FinFET with high-K gate dielectric materials in 5 nm technology: a simulation study
The rapid advancement in nanoscale devices demands innovative gate dielectric materials
to replace traditional Silicon dioxide. This paper investigates the electrical behavior and …
to replace traditional Silicon dioxide. This paper investigates the electrical behavior and …
Dopingless 1T DRAM: Proposal, design, and analysis
A James, S Saurabh - IEEE Access, 2019 - ieeexplore.ieee.org
In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge
plasma concept. The proposed device employs a misaligned double-gate architecture to …
plasma concept. The proposed device employs a misaligned double-gate architecture to …
Core-insulator embedded nanosheet field-effect transistor for suppressing device-to-device variations
D Son, H Lee, H Kim, JH Ahn, S Kim - Scientific Reports, 2024 - nature.com
Nanosheet field-effect transistors (NSFETs) have attracted considerable attention for their
potential to achieve improved performance and energy efficiency compared to traditional …
potential to achieve improved performance and energy efficiency compared to traditional …
Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors
AV Arun, PS Sreelekshmi, J Jacob - Microelectronics Journal, 2022 - Elsevier
In this paper, a dopingless DRAM based on work function engineered Tunnel field effect
transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF …
transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF …
A Feedback Self-adaptive Body Biasing-based RF-DC Rectifier for Highly-sensitive RF Energy Harvesting
Using radio frequency (RF) energy to power Internet of Things (IoT) devices over extended
distances poses a challenge due to limited input power. As we move farther from the source …
distances poses a challenge due to limited input power. As we move farther from the source …
Process and simulation design of silicon-on-insulator (SOI) NMOS
ZF Chen, YS Lai, CM Huang, YH Wang… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
As CMOS devices continue to shrink, traditional bulk-based MOSFETs are facing physical
limits. In addition, the process compatibility of SOI and bulk has been confirmed. We develop …
limits. In addition, the process compatibility of SOI and bulk has been confirmed. We develop …