Chip floorplanning is the engineering task of designing the physical layout of a computer
chip. Despite five decades of research 1, chip floorplanning has defied automation, requiring …

Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Force-directed algorithms have been developed over the last 50 years and used in many
application fields, including information visualisation, biological network visualisation …

Macro placement is a critical very large-scale integration (VLSI) physical design problem
that significantly impacts the design power-performance-area (PPA) metrics. This paper …

We propose a self-contained, flat, quadratic global placer that is simpler than existing
placers and easier to integrate into timing-closure flows. It maintains lower-bound and upper …

Physical design and production of Integrated Circuits (IC) is becoming increasingly more
challenging as the sophistication in IC technology is steadily increasing. Placement has …

We propose a new multilevel framework for large-scale placement called MAPLE that
respects utilization constraints, handles movable macros and guides the transition between …

A wirelength-driven placer without considering routability could introduce irresolvable
routing-congested placements. Therefore, it is desirable to develop an effective routability …

A placer without considering modern technology and region constraints could generate
solutions with irresolvable detailed-routing (DR) violations or even illegal solutions. This …

Due to the significant mismatch between existing wirelength models and the congestion
objective in placement, considering routability during placement is particularly significant for …