Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

V Narula, M Agarwal - Semiconductor Science and Technology, 2019 - iopscience.iop.org
This paper proposes a p-type double gate junctionless field effect transistor having opposite
doping in the core with that of the silicon body referring to rectangular core–shell (RCS) …

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

V Narula, M Agarwal - Semiconductor science and technology, 2020 - iopscience.iop.org
A rectangular core is inserted in double gate junctionless transistor (DGJLT) which
separates the top shell and bottom shell in the device called as rectangular core–shell …

Topography simulation of novel processing techniques

L Filipovic - 2012 - repositum.tuwien.at
Topography simulations allow for a visualization of semiconductor surfaces as well as the
interfaces between various material regions after a given processing step. Topography …

Femtomolar dengue virus type-2 DNA detection in back-gated silicon nanowire field-effect transistor biosensor

WABZ Abidin, MNM Nor, MKM Arshad… - Current …, 2022 - ingentaconnect.com
Background: Dengue is known as the most severe arboviral infection in the world spread by
Aedes aegypti. However, conventional and laboratory-based enzyme-linked immunosorbent …

Impact of KOH etching on nanostructure fabricated by local anodic oxidation method

A Dehzangi, F Larki, BY Majlis, MG Naseri… - International Journal of …, 2013 - Elsevier
In this letter, we investigate the impact of potassium hydroxide (KOH) etching procedure on
Silicon nanostructure fabricated by Atomic force microscopy on P-type Silicon-on-insulator …

Non‐uniform doping dependent electrical parameters of dual‐metal gate all around junctionless accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET)

S Gupta, N Pandey, RS Gupta - International Journal of …, 2024 - Wiley Online Library
This paper presents an analytical analysis of a dual‐metal gate all around junctionless
accumulation‐mode nanowire FET (DMGAA‐JAM‐NWFET) possessing a horizontal‐like …

Impact of parameter variation in fabrication of nanostructure by atomic force microscopy nanolithography

A Dehzangi, F Larki, SD Hutagalung… - PloS one, 2013 - journals.plos.org
In this letter, we investigate the fabrication of Silicon nanostructure patterned on lightly
doped (1015 cm− 3) p-type silicon-on-insulator by atomic force microscope nanolithography …

[HTML][HTML] Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

F Larki, A Dehzangi, A Abedini… - Beilstein journal of …, 2012 - beilstein-journals.org
A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (10 15)
silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy …

Threshold voltage of p-type triple-gate junctionless transistors

TA Oproglidis, DH Tassis, A Tsormpatzoglou… - Solid-State …, 2022 - Elsevier
The threshold voltage of rectangular p-type triple-gate junctionless transistors (JLTs) is
studied experimentally using the transconductance derivative (dg m/dV g) method, after …

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High …

J Singh, RK Chauhan - physica status solidi (a), 2023 - Wiley Online Library
Junctionless metal–oxide‐semiconductor field‐effect transistors (MOSFETs) have emerged
as a promising alternative to conventional MOSFETs, offering simplified fabrication and …