Slim noc: A low-diameter on-chip network topology for high energy efficiency and scalability

M Besta, SM Hassan, S Yalamanchili… - ACM SIGPLAN …, 2018 - dl.acm.org
Emerging chips with hundreds and thousands of cores require networks with unprecedented
energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on …

ShortPath: A network-on-chip router with fine-grained pipeline bypassing

A Psarras, I Seitanidis, C Nicopoulos… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
Scalable Network-on-Chip (NoC) architectures should achieve high-throughput and low-
latency operation without exceeding the stringent area/energy constraints of modern …

Deadline-aware and energy-efficient dynamic task mapping and scheduling for multicore systems based on wireless network-on-chip

A Dehghani, S Fadaei, B Ravaei… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Hybrid Wireless Network-on-Chip (HWNoC) architecture has been introduced as a
promising communication infrastructure for multicore systems. HWNoC-based multicore …

SDNoC: Software defined network on a chip

K Berestizshevsky, G Even, Y Fais… - Microprocessors and …, 2017 - Elsevier
We present a novel network-on-chip (NoC) architecture, called SDNoC, that is based on a
hybrid hardware/software approach. This approach is based on a few principles used in …

Networks-on-chip with double-data-rate links

A Psarras, S Moisidis, C Nicopoulos… - … on Circuits and …, 2017 - ieeexplore.ieee.org
The need for higher throughput and lower communication latency in modern networks-on-
chip (NoC) has led to low-and high-radix topologies that exploit the speed provided by on …

Development of a universal adaptive fast algorithm for the synthesis of circulant topologies for networks-on-chip implementations

AY Romanov, II Romanova… - 2018 IEEE 38th …, 2018 - ieeexplore.ieee.org
In this article, the feasibility of realization of optimal circulant topologies in networks-on-chip
was researched. The software for automating the synthesis of circulant topologies of various …

A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

A Dehghani, K Jamshidi - The Journal of Supercomputing, 2015 - Springer
Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints
in the traditional electrical interconnections. However, the occurrence of faults has become …

A low-power network-on-chip architecture for tile-based chip multi-processors

A Psarras, J Lee, P Mattheakis, C Nicopoulos… - Proceedings of the 26th …, 2016 - dl.acm.org
Technology scaling of tiled-based CMPs reduces the physical size of each tile and
increases the number of tiles per die. This trend directly impacts the on-chip interconnect; …

The dataset for optimal circulant topologies

A Romanov - Big Data and Cognitive Computing, 2023 - mdpi.com
This article presents software for the synthesis of circulant graphs and the dataset obtained.
An algorithm and new methods, which increase the speed of finding optimal circulant …

A design flow for an optimized congestion-aware application-specific wireless network-on-chip architecture

A Dehghani - Future Generation Computer Systems, 2020 - Elsevier
Abstract Wireless Networks-on-Chip (WiNoC) architecture has emerged as an alternative
communication infrastructure for the conventional wire-line NoC to achieve higher …