FinFETs: From devices to architectures
D Bhattacharya, NK Jha - Advances in Electronics, 2014 - Wiley Online Library
Since Moore's law driven scaling of planar MOSFETs faces formidable challenges in the
nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to …
nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to …
Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part II—Results and figures of merit
In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and
topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed …
topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed …
Tunnel FETs for ultralow voltage digital VLSI circuits: Part I—Device–circuit interaction and evaluation at device level
D Esseni, M Guglielmini, B Kapidani… - … Transactions on Very …, 2014 - ieeexplore.ieee.org
This paper and the companion work present the results of a comparative study between the
tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting …
tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting …
[图书][B] Introduction to VLSI systems: a logic, circuit, and system perspective
MB Lin - 2011 - taylorfrancis.com
With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip
(SoC) has become an essential technique to reduce product cost. With this progress and …
(SoC) has become an essential technique to reduce product cost. With this progress and …
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
M Alioto - IEEE Transactions on Very Large Scale Integration …, 2010 - ieeexplore.ieee.org
In this paper, issues related to the physical design and layout density of FinFET standard
cells are discussed. Analysis significantly extends previous analyses, which considered the …
cells are discussed. Analysis significantly extends previous analyses, which considered the …
Radiation Effects in VLSI Circuits-Part II: Hardening Techniques
A Kannaujiya, AP Shah - IETE Technical Review, 2024 - Taylor & Francis
This work presents a comprehensive review on radiation hardening techniques aimed at
enhancing the resilience of VLSI circuits against soft errors. The study covers a wide …
enhancing the resilience of VLSI circuits against soft errors. The study covers a wide …
Tunnel FETs for ultra-low voltage digital VLSI circuits: Part II–Evaluation at circuit level and design perspectives
M Alioto, D Esseni - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
In Part II of this paper, the potential of tunnel FETs (TFETs) for ultra-low voltage (ULV)/ultra-
low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of …
low power (ULP) operation at 32-nm node is investigated through Verilog-A simulations of …
Understanding the basic advantages of bulk FinFETs for sub-and near-threshold logic circuits from device measurements
This study aims to understand the potential of bulk FinFET technology from the perspective
of sub-and near-threshold logic circuits down to 100-mV bias voltage. Measurements are …
of sub-and near-threshold logic circuits down to 100-mV bias voltage. Measurements are …
Comparative soft error evaluation of layout cells in FinFET technology
This work presents a comparative soft error evaluation of logic gates in bulk FinFET
technology from 65-down to 32-nm technology generations. Single Event Transients …
technology from 65-down to 32-nm technology generations. Single Event Transients …
A voltage-based leakage current calculation scheme and its application to nanoscale MOSFET and FinFET standard-cell designs
Z Abbas, A Mastrandrea… - IEEE Transactions on Very …, 2014 - ieeexplore.ieee.org
Logic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are
relevant for the dramatic speed advantage with respect to analog SPICE-level simulation …
relevant for the dramatic speed advantage with respect to analog SPICE-level simulation …