Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Optimizing for routability during FPGA placement is becoming increasingly important, as
failure to spread and resolve congestion hotspots throughout the chip, especially in the case …

As a good tradeoff between central processing unit (CPU) and application specific
integrated circuit (ASIC), field-programmable gate array (FPGA) is becoming more widely …

As field-programmable gate array (FPGA) architectures continue to evolve and become
more complex, the heterogeneity and clock constraints imposed by modern FPGAs have …

Beyond ordinary graphs, hypergraphs are a graph representation to flexibly express
complex multilateral relationships between entities. Hypergraph processing can be used to …

Hypergraph processing has emerged as a powerful approach for analyzing complex
multilateral relationships among multiple entities. Past research on building hypergraph …

We present a new algorithm for VLSI placement. Our tool BonnPlace incorporates a
partitioning-based legalization into a force-directed loop by iteratively pulling circuits …

In this article we propose an effective algorithm flow to handle modern large-scale mixed-
size placement, both with and without geometry constraints. The basic idea is to use …

Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its
result, paired with the outcome of the routing procedure can be the decisive factor in …

Circuit clustering is usually done through discrete optimizations, with the purpose of circuit
size reduction or design-specific cluster formation. Specifically, we are interested in the multi …