An asynchronous low power and high performance VLSI architecture for Viterbi decoder implemented with quasi delay insensitive templates

TK Devi, S Palaniappan - The Scientific World Journal, 2015 - Wiley Online Library
Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in
digital communication systems. For decoding of convolutional codes at the receiver end …

A low power asynchronous Viterbi decoder using minimum transition hybrid register exchange method

SK Tadse, SL Haridas - 2017 International Conference On …, 2017 - ieeexplore.ieee.org
Todays world is digital and therefore digital communication plays a vital role in
communication systems. Viterbi algorithm invented by Andrew J. Viterbi is widely used for …

[PDF][PDF] Design of Asynchronous Viterbi Decoder using Hybrid Register Exchange Method for Low Power Applications: A Review

NS Kalaskar - Sr. No Name Page - researchgate.net
This paper describe the design of viterbi decoder using various methods. Hybrid Register
(HREM) exchange method which is the combination of design traceback (TB) & register …

[PDF][PDF] A REVIEW ON LOW POWER DESIGN FOR ASYNCHRONOUS VITERBI DECODER

MNS Wange, PG Scholar, SL Haridas… - 2014 - Citeseer
In digital communication system, channel coding techniques are mostly use convolutional
codes for wireless Applications. For decoding the convolutional codes Viterbi decoder is …

[PDF][PDF] DESIGN OF VITERBI DECODER FOR UNDERWATER MARINE RECEIVERS USING MULTI-THRESHOLD NULL CONVENTION LOGIC (MTNCL)

S Jyothula, AU Maheswari - Defence S&T Technical Bulletin, 2017 - stride.gov.my
In this paper, we develop a Viterbi decoder for underwater ITU-V. 34 standard marine
receivers. In order to have low power and to accomplish faithful quality of transmission …

[图书][B] Design of a low power asynchronous Viterbi decoder for wireless communications

P Deshpande - 2016 - search.proquest.com
Rapid developments in the communications field have created a rising demand for low
power, high speed, and low weight communication devices. The current project presents the …

[PDF][PDF] Design of Asynchronous Viterbi Decoder using Bundled Data Protocol for Low Power Consumption

NR Chambhare, ST Kalambe - academia.edu
This paper proposes a review on the designing of Asynchronous Viterbi Decoder. In order to
reduce the power consumption and increase the speed, it is necessary to design …

[引用][C] Design of Asynchronous Viterbi Decoder for Low Power Applications

SK Tadse - International Journal on Recent and Innovation Trends …

[引用][C] Design of Asynchronous Viterbi Decoder using Hybrid Register Exchange method for Low Power Application

MMN Narnaware, SK Tadse

[引用][C] Design of Asynchronous Viterbi Decoder using Hybrid Register Exchange Method for Low Power Applications

PM Chandel, MN Thakre, GD Korde