A 1-to-1-kHz, 4.2-to-544-nW, multi-level comparator based level-crossing ADC for IoT applications

Y Hou, K Yousef, M Atef, G Wang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This brief presents the design of an ultra-low power level-crossing analog-to-digital
converter (LC-ADC) for IoT and biomedical applications. The proposed LC-ADC utilizes only …

Why analog-to-information converters suffer in high-bandwidth sparse signal applications

O Abari, F Lim, F Chen… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
In applications where signal frequencies are high, but information bandwidths are low,
analog-to-information converters (AICs) have been proposed as a potential solution to …

Event-driven GHz-range continuous-time digital signal processor with activity-dependent power dissipation

M Kurchuk, C Weltin-Wu, D Morche… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of the
limitations of conventional digital and analog implementations. Per-edge digital signal …

A nonuniform sampling ADC architecture with reconfigurable digital anti-aliasing filter

TF Wu, S Dey, MSW Chen - … on Circuits and Systems I: Regular …, 2016 - ieeexplore.ieee.org
This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture
that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital …

A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter

D Hand, MSW Chen - 2012 IEEE Global Communications …, 2012 - ieeexplore.ieee.org
This work proposes a non-uniform sampling analog-to-digital converter (ADC) architecture
that embeds an alias-free filter in the asynchronous digital domain to relax the requirements …

A 0.5 V signal-specific continuous-time level-crossing ADC with charge sharing

Y Li, D Zhao, MN Van Dongen… - 2011 IEEE Biomedical …, 2011 - ieeexplore.ieee.org
This paper presents a novel continuous-time level-crossing analog-to-digital converter (LC-
ADC) targeted at biomedical signal sensing applications. The conventional digital-to-analog …

Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications

C Vezyrtzis, Y Tsividis… - 2012 IEEE 30th …, 2012 - ieeexplore.ieee.org
A calibrated delay line is a key component in many modern digital systems. Traditionally,
these lines are designed as real-time pipelines with static granularity, fine enough to handle …

Advanced Non-Uniform Sampling Techniques for Energy-Efficient Data Acquisition

M Elmi - 2024 - era.library.ualberta.ca
With the growing demand for power-efficient data acquisition systems, particularly in low-
power sensor applications that rely on energy harvesting or limited energy stored in small …

Systems and methods for implementing error-shaping alias-free asynchronous flipping analog to digital conversion

SP Patil, Y Tsividis, D Morche, A Ratiu - US Patent 9,300,315, 2016 - Google Patents
A programmable, quantization error spectral shaping, alias-free asynchronous analog-to-
digital converter (ADC) is provided. The ADC can be used for clock-less, continuous-time …

A decision feedback equalizer with channel-dependent power consumption for 60-GHz receivers

I Sourikopoulos, A Frappe, A Kaiser… - 2014 IEEE International …, 2014 - ieeexplore.ieee.org
The design of a baseband decision feedback equalizer, featuring a continuous-time digital
delay line, is discussed within the context of a wireless, Line-Of-Sight, communication …