A survey of research into mixed criticality systems
This survey covers research into mixed criticality systems that has been published since
Vestal's seminal paper in 2007, up until the end of 2016. The survey is organised along the …
Vestal's seminal paper in 2007, up until the end of 2016. The survey is organised along the …
[PDF][PDF] Mixed criticality systems-a review
This review covers research on the topic of mixed criticality systems that has been published
since Vestal's 2007 paper. It covers the period up to end of 2021. The review is organised …
since Vestal's 2007 paper. It covers the period up to end of 2021. The review is organised …
A deeper look into rowhammer's sensitivities: Experimental analysis of real dram chips and implications on future attacks and defenses
RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (ie,
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
In defense of soft-assignment coding
In object recognition, soft-assignment coding enjoys computational efficiency and
conceptual simplicity. However, its classification performance is inferior to the newly …
conceptual simplicity. However, its classification performance is inferior to the newly …
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms
DRAM consists of multiple resources called banks that can be accessed in parallel and
independently maintain state information. In Commercial Off-The-Shelf (COTS) multicore …
independently maintain state information. In Commercial Off-The-Shelf (COTS) multicore …
Multi-core devices for safety-critical systems: A survey
Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …
critical systems, enabling the on-chip integration of functions of different criticality. This …
Worst case analysis of DRAM latency in multi-requestor systems
ZP Wu, Y Krish, R Pellizzoni - 2013 IEEE 34th Real-Time …, 2013 - ieeexplore.ieee.org
As multi-core systems are becoming more popular in real-time embedded systems, strict
timing requirements for accessing shared resources must be met. In particular, a detailed …
timing requirements for accessing shared resources must be met. In particular, a detailed …
Parallelism-aware memory interference delay analysis for COTS multicore systems
In modern Commercial Off-The-Shelf (COTS) mul-ticore systems, each core can generate
many parallel memory requests at a time. The processing of these parallel requests in the …
many parallel memory requests at a time. The processing of these parallel requests in the …
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems
Mixed-time critical systems are real-time systems that accommodate both hard real-time
(HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase …
(HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase …
Identifying the sources of unpredictability in COTS-based multicore systems
COTS-based multicores are now the preferred choice for hosting embedded applications
owing to their immense computational capabilities, small form factor and low power …
owing to their immense computational capabilities, small form factor and low power …