In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and …
The low communication bandwidth between memory and processing units in conventional
von Neumann machines does not support the requirements of emerging applications that …
von Neumann machines does not support the requirements of emerging applications that …
Testability and dependability of AI hardware: Survey, trends, challenges, and perspectives
F Su, C Liu, HG Stratigopoulos - IEEE Design & Test, 2023 - ieeexplore.ieee.org
Hardware realization of artificial intelligence (AI) requires new design styles and even
underlying technologies than those used in traditional digital processors or logic circuits …
underlying technologies than those used in traditional digital processors or logic circuits …
Snr: S queezing n umerical r ange defuses bit error vulnerability surface in deep neural networks
E Ozen, A Orailoglu - ACM Transactions on Embedded Computing …, 2021 - dl.acm.org
As deep learning algorithms are widely adopted, an increasing number of them are
positioned in embedded application domains with strict reliability constraints. The …
positioned in embedded application domains with strict reliability constraints. The …
Reliability evaluation and analysis of FPGA-based neural network acceleration system
Prior works typically conducted the fault analysis of neural network accelerator computing
arrays with simulation and focused on the prediction accuracy loss of the neural network …
arrays with simulation and focused on the prediction accuracy loss of the neural network …
Stuck-at-fault tolerant schemes for memristor crossbar array-based neural networks
In this study, a circuit technique and training algorithm that minimizes the effect of stuck-at-
faults (SAFs) within a memristor crossbar array of neural networks (NNs) are presented. To …
faults (SAFs) within a memristor crossbar array of neural networks (NNs) are presented. To …
Learning to train CNNs on faulty ReRAM-based manycore accelerators
The growing popularity of convolutional neural networks (CNNs) has led to the search for
efficient computational platforms to accelerate CNN training. Resistive random-access …
efficient computational platforms to accelerate CNN training. Resistive random-access …
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators
Graph Neural Networks (GNNs) have achieved remarkable accuracy in cognitive tasks such
as predictive analytics on graph-structured data. Hence, they have become very popular in …
as predictive analytics on graph-structured data. Hence, they have become very popular in …
Training modern deep neural networks for memory-fault robustness
GB Hacene, F Leduc-Primeau… - … on Circuits and …, 2019 - ieeexplore.ieee.org
Because deep neural networks (DNNs) rely on a large number of parameters and
computations, their implementation in energy-constrained systems is challenging. In this …
computations, their implementation in energy-constrained systems is challenging. In this …
A non-idealities aware software–hardware co-design framework for edge-AI deep neural network implemented on memristive crossbar
In this work, a non-idealities aware software-hardware co-design framework for deep neural
network (DNN) implemented on memristive crossbar is presented. The device level non …
network (DNN) implemented on memristive crossbar is presented. The device level non …
Low-cost error detection in deep neural network accelerators with linear algorithmic checksums
E Ozen, A Orailoglu - Journal of Electronic Testing, 2020 - Springer
The widespread adoption of deep neural networks in safety-critical systems necessitates the
examination of the safety issues raised by hardware errors. The appropriateness of the …
examination of the safety issues raised by hardware errors. The appropriateness of the …