A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS
S Lu, S Xie, L Mao, R Song, N Zhang - Microelectronics Journal, 2023 - Elsevier
This paper analyzed the causes of phase jitter in four-level pulse amplitude modulation
(PAM4) optical receiver (ORX), and a modified architecture was proposed. An optimized …
(PAM4) optical receiver (ORX), and a modified architecture was proposed. An optimized …
Far-End Crosstalk Cancellation With MIMO OFDM for> 200 Gb/s ADC-Based Serial Links
G Kim - IEEE Transactions on Circuits and Systems II: Express …, 2022 - ieeexplore.ieee.org
This brief presents an area-and power-efficient far-end crosstalk (FEXT) cancellation
scheme with multi-input multi-output (MIMO) orthogonal frequency-division multiplexing …
scheme with multi-input multi-output (MIMO) orthogonal frequency-division multiplexing …
A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE
W Han, Y Wang, J Wang - IEICE Electronics Express, 2021 - jstage.jst.go.jp
This paper presents a 56-Gbps four-level pulse amplitude modulation (PAM4) quarter-rate
receiver based on amplitude rectification. Compared with the conventional three-comparator …
receiver based on amplitude rectification. Compared with the conventional three-comparator …
A 25.6-Gb/s interface employing PAM-4-based four-channel multiplexing and cascaded clock and data recovery circuits in ring topology for high-bandwidth and large …
T Toi, J Wadatsumi, H Kobayashi… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface
for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash …
for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash …
Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics
In high-speed serial link, the analog-digital converter (ADC)-based receiver (RX)
architecture has been widely applied with 4-level pulse amplitude modulation (PAM-4) for> …
architecture has been widely applied with 4-level pulse amplitude modulation (PAM-4) for> …
Link bit-error-rate requirement analysis for deep neural network accelerators
In convolutional neural network (CNN) accelerators, the dominant power consumption is
caused by the access of external data memory. In addition, power and area occupied by I/O …
caused by the access of external data memory. In addition, power and area occupied by I/O …