NoC routing protocols–objective-based classification
AB Gabis, M Koudil - Journal of Systems Architecture, 2016 - Elsevier
Abstract NoCs (Network on Chips) are the most popular interconnection mechanism used
for systems that require flexibility, extensibility and low power consumption. However …
for systems that require flexibility, extensibility and low power consumption. However …
EbDa: A new theory on design and verification of deadlock-free interconnection networks
M Ebrahimi, M Daneshtalab - Proceedings of the 44th Annual …, 2017 - dl.acm.org
Freedom from deadlock is one of the most important issues when designing routing
algorithms in on-chip/off-chip networks. Many works have been developed upon Dally's …
algorithms in on-chip/off-chip networks. Many works have been developed upon Dally's …
Efficient design-for-test approach for networks-on-chip
To achieve high reliability in on-chip networks, it is necessary to test the network
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …
TSV-OCT: A scalable online multiple-TSV defects localization for real-time 3-D-IC systems
In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and
operating phases, most of the existing methods use a dedicated testing mechanism with …
operating phases, most of the existing methods use a dedicated testing mechanism with …
REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip
Y Ouyang, D Xu, Z Chen, R Chen, W Zhou… - Microelectronics …, 2022 - Elsevier
Currently, on-chip routers consume the majority of the power budget. Moreover, the static
power consumption has taken up a significant fraction of the total power consumption in the …
power consumption has taken up a significant fraction of the total power consumption in the …
Performance-aware test scheduling for diagnosing coexistent channel faults in topology-agnostic networks-on-chip
High--performance multiprocessor SoCs used in practice require a complex network-on-chip
(NoC) as communication architecture, and the channels therein often suffer from various …
(NoC) as communication architecture, and the channels therein often suffer from various …
Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip
B Bhowmik - Microelectronics Reliability, 2023 - Elsevier
The guaranteed delivery of application packets from source to destination in a network-on-
chip (NoC) is increasingly becoming an essential design issue. Channel faults may cause a …
chip (NoC) is increasingly becoming an essential design issue. Channel faults may cause a …
Compact piecewise linear model based temperature control of multicore systems considering leakage power
H Wang, L Hu, X Guo, Y Nie… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Temperature control of the new-generation integrated multicore system is challenging. This
is because the leakage power, which is significant in modern systems, is nonlinearly related …
is because the leakage power, which is significant in modern systems, is nonlinearly related …
Component Dependencies Based Network-on-Chip Test
L Huang, T Zhao, Z Wang, J Zhan… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
On-line test of NoC is essential for its reliability. This paper proposed an integral test solution
for on-line test of NoC to reduce the test cost and improve the reliability of NOC. The test …
for on-line test of NoC to reduce the test cost and improve the reliability of NOC. The test …
Visualnoc: A visualization and evaluation environment for simulation and mapping
Simulation is the most common approach to evaluate Network on Chip (NoC) designs and
many simulators at different abstraction levels have been developed so far. However …
many simulators at different abstraction levels have been developed so far. However …