Domino logic synthesis minimizing crosstalk
KW Kim, U Narayanan, SM Kang - Proceedings of the 37th Annual …, 2000 - dl.acm.org
Based on the new concept of crosstalk immunity set (CIS), procedures to minimize
capacitive cross-coupling effects are developed for domino logic circuit. The nets in a …
capacitive cross-coupling effects are developed for domino logic circuit. The nets in a …
Noise-aware power optimization for on-chip interconnect
KW Kim, SO Jung, U Narayanan, CL Liu… - Proceedings of the 2000 …, 2000 - dl.acm.org
Realization of high-performance domino logic depends strongly on energy-efficient and
noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the …
noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the …
Crosstalk noise minimization in domino logic design
KW Kim, SM Kang - … Transactions on Computer-Aided Design of …, 2001 - ieeexplore.ieee.org
Based on the new concept of crosstalk immunity set (CIS), procedures to minimize
capacitive crosscoupling effects are developed for domino logic circuit. The nets in a CIS are …
capacitive crosscoupling effects are developed for domino logic circuit. The nets in a CIS are …
Noise-aware interconnect power optimization in domino logic synthesis
KW Kim, SO Jung, U Narayanan… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
Realization of high-performance domino logic depends strongly on energy-efficient and
noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize …
noise-tolerant interconnect design in ultradeep submicrometer processes. We characterize …
[PDF][PDF] Minimum Crosstalk Channel Routing
S Chandhrasri, W Sirisaengtaksin - EE680, Spring, 2002 - Citeseer
The space between interconnects in a VLSI chip become closer as the VLSI technology
rapidly evolves. Moreover, advancements in VLSI technology have dramatically increased …
rapidly evolves. Moreover, advancements in VLSI technology have dramatically increased …
[图书][B] Reliable low-power solution for high-performance VLSI circuit design
KW Kim - 2001 - search.proquest.com
High-performance circuit design in gigahertz clock frequency requires extensive use of
dynamic logic. Prevalent application of dynamic logic provides high speed but can entail …
dynamic logic. Prevalent application of dynamic logic provides high speed but can entail …
[PDF][PDF] Noise-Aware Power Optimization for On-Chip Interconnect
SOJ Ki-WookKim, CL UnniNarayanan, SM Kang - 2000 - websrv.cecs.uci.edu
Realization of high-performance domino logic depends strongly on energy-efficient and
noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the …
noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the …