Integrations and challenges of novel high-k gate stacks in advanced CMOS technology
G He, L Zhu, Z Sun, Q Wan, L Zhang - Progress in Materials Science, 2011 - Elsevier
Due to the limitations in conventional complementary metal–oxide–semiconductor (CMOS)
scaling technology in recent years, innovation in transistor structures and integration of …
scaling technology in recent years, innovation in transistor structures and integration of …
High-/spl kappa//metal-gate stack and its MOSFET characteristics
R Chau, S Datta, M Doczy, B Doyle… - IEEE Electron …, 2004 - ieeexplore.ieee.org
We show experimental evidence of surface phonon scattering in the high-/spl
kappa/dielectric being the primary cause of channel electron mobility degradation. Next, we …
kappa/dielectric being the primary cause of channel electron mobility degradation. Next, we …
An adjustable work function technology using Mo gate for CMOS devices
R Lin, Q Lu, P Ranade, TJ King… - IEEE Electron Device …, 2002 - ieeexplore.ieee.org
Nitrogen implantation of Mo gate was used to fabricate MOS capacitors and CMOS
transistors. Initial studies demonstrate that the work function of Mo is sensitive to nitrogen …
transistors. Initial studies demonstrate that the work function of Mo is sensitive to nitrogen …
Study and analysis of advanced 3D multi-gate junctionless transistors
As the IC technology is evolving very rapidly, the feature size of the device has been
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
migrating to sub-nanometre regime for achieving the high packing density. To continue with …
Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications
This manuscript for the first time investigates the effect of Dual Metal on Gate Junctionless
Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. The entire analysis is …
Nanosheet FET (DMG-JL-NSFET) for analog/RF applications. The entire analysis is …
Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric
YC Yeo, Q Lu, P Ranade, H Takeuchi… - IEEE Electron …, 2001 - ieeexplore.ieee.org
We report the first demonstration of a dual-metal gate complementary metal oxide
semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate …
semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate …
Wide range work function modulation of binary alloys for MOSFET application
BY Tsui, CF Huang - IEEE Electron Device Letters, 2003 - ieeexplore.ieee.org
This paper explores the characteristics of the binary alloys Ta-Pt and Ta-Ti for gate electrode
application. With a proper composition of high and low work function metals, the work …
application. With a proper composition of high and low work function metals, the work …
MOSFET devices with polysilicon on single-layer HfO/sub 2/high-K dielectrics
L Kang, K Onishi, Y Jeon, BH Lee… - … Digest. IEDM (Cat …, 2000 - ieeexplore.ieee.org
MOSFETs and MOSCAPs of a single-layer thin HfO/sub 2/gate dielectric with dual
polysilicon gate were fabricated with self-aligned process and characterized. Polysilicon and …
polysilicon gate were fabricated with self-aligned process and characterized. Polysilicon and …
A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film
H Wakabayashi, Y Saito, K Takeuchi… - … on Electron Devices, 2001 - ieeexplore.ieee.org
A novel dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film
is described. It is based on a new finding that threshold voltage (V/sub th/) depends on the …
is described. It is based on a new finding that threshold voltage (V/sub th/) depends on the …
Investigation of short channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET
FinFETs are popular and forefront runner in integrated circuits (ICs) technology due to
exceptional scalability and suppressed short channel effects (SCEs). The bottom spacer …
exceptional scalability and suppressed short channel effects (SCEs). The bottom spacer …