Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)
A Ben Ahmed, A Ben Abdallah - The Journal of Supercomputing, 2013 - Springer
Despite the higher scalability and parallelism integration offered by Network-on-Chip (NoC)
over the traditional shared-bus based systems, it is still not an ideal solution for future large …
over the traditional shared-bus based systems, it is still not an ideal solution for future large …
Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures
Three-dimensional IC technology offers greater device integration and shorter interlayer
interconnects. In order to take advantage of these attributes, 3D stacked mesh architecture …
interconnects. In order to take advantage of these attributes, 3D stacked mesh architecture …
High-performance and fault-tolerant 3D NoC-bus hybrid architecture using ARB-NET-based adaptive monitoring platform
The emerging three-dimensional integrated circuits (3D-ICs) achieve greater device
integration and enhanced system performance at lower cost and reduced area footprint …
integration and enhanced system performance at lower cost and reduced area footprint …
Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip
Increasing the number of cores over a 2D plane is not efficient in hyper-core systems due to
long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology …
long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology …
PVS-NoC: Partial virtual channel sharing NoC architecture
K Latif, AM Rahmani, L Guang… - … and Network-Based …, 2011 - ieeexplore.ieee.org
A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial
VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve …
VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve …
KBMA: A knowledge‐based multi‐objective application mapping approach for 3D NoC
A Alagarsamy, L Gopalakrishnan… - IET Computers & Digital …, 2019 - Wiley Online Library
Due to increased demands for communication at low power, an efficient application
mapping has become vital in the area of network on chip (NoC). Optimisation of architectural …
mapping has become vital in the area of network on chip (NoC). Optimisation of architectural …
Deadlock-recovery support for fault-tolerant routing algorithms in 3d-noc architectures
AB Ahmed, AB Ahmed… - 2013 IEEE 7th …, 2013 - ieeexplore.ieee.org
In this paper, we present a low-cost deadlock-recovery technique for fault-tolerant routing
algorithms in 3-dimensional Networks-on-Chip (3D-NoC) systems, called Random-Access …
algorithms in 3-dimensional Networks-on-Chip (3D-NoC) systems, called Random-Access …
An overview of RISC vs. CISC
AD George - … The Twenty-Second Southeastern Symposium on …, 1990 - computer.org
In this paper, we present a low-cost deadlock-recovery technique for fault-tolerant routing
algorithms in 3-dimensional Networks-on-Chip (3D-NoC) systems, called Random-Access …
algorithms in 3-dimensional Networks-on-Chip (3D-NoC) systems, called Random-Access …
Lastz: An ultra optimized 3d networks-on-chip architecture
3D IC technology enables NoC architectures to offer greater device integration and shorter
interlayer interconnects. The primary 3D NoC architectures such as Symmetric 3D Mesh …
interlayer interconnects. The primary 3D NoC architectures such as Symmetric 3D Mesh …
BBVC-3D-NoC: an efficient 3D NoC architecture using bidirectional bisynchronous vertical channels
In this paper, a 3D NoC architecture based on Bidirectional Bisynchronous Vertical
Channels (BBVC) is proposed as a solution to mitigate area footprints of vertical …
Channels (BBVC) is proposed as a solution to mitigate area footprints of vertical …