Review of nanosheet metrology opportunities for technology readiness
Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured
the focus of the semiconductor industry and have been identified as the lead architecture to …
the focus of the semiconductor industry and have been identified as the lead architecture to …
Extracting dimensional parameters of gratings produced with self-aligned multiple patterning using grazing-incidence small-angle x-ray scattering
Background: To ensure consistent and high-quality semiconductor production at future logic
nodes, additional metrology tools are needed. For this purpose, grazing-incidence small …
nodes, additional metrology tools are needed. For this purpose, grazing-incidence small …
Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?
We report a systematic study of the feasibility of using directed self-assembly (DSA) in real
product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design …
product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design …
Bayesian dropout approximation in deep learning neural networks: analysis of self-aligned quadruple patterning
Background Predictive estimates of the final process outcome (s) of multistep, coupled
processes can be difficult to make based on data measured at the various process steps …
processes can be difficult to make based on data measured at the various process steps …
AFM characterization for gate-all-around (GAA) devices
As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the
candidate technology for future nodes, several key process points remain difficult to …
candidate technology for future nodes, several key process points remain difficult to …
Substrate, metrology apparatus and associated methods for a lithographic process
A Verma, HAJ Cramer, T Theeuwes… - US Patent …, 2020 - Google Patents
A substrate having a plurality of features for use in measuring a parameter of a device
manufacturing process and associated methods and apparatus. The measurement is by …
manufacturing process and associated methods and apparatus. The measurement is by …
[PDF][PDF] Extracting Dimensional Parameters of Gratings Produced with Self-Aligned Multiple Patterning Using GISAXS
M Pflüger12, RJ Kline, AF Herrero… - arXiv preprint arXiv …, 2019 - tsapps.nist.gov
Background: To ensure consistent and high-quality semiconductor production at future logic
nodes, additional metrology tools are needed. For this purpose, grazing-incidence small …
nodes, additional metrology tools are needed. For this purpose, grazing-incidence small …
[PDF][PDF] Experiment Management Wafer and Wafer Group Graph
TD Carvalho - 2020 - repositorio-aberto.up.pt
In the 21st century, Industry 4.0 emerged as a promising approach to face global
competition. However, its requirements demand profound changes in manufacturing …
competition. However, its requirements demand profound changes in manufacturing …
Process Optimization by Clamped Monte Carlo Distribution
Techniques for semiconductor process flow disposition opti mization using clamped Monte
Carlo distribution are pro vided. In one aspect, a method for optimizing a semicon ductor …
Carlo distribution are pro vided. In one aspect, a method for optimizing a semicon ductor …
Substrate, metrology apparatus and associated methods for a lithographic process
A Verma, HAJ Cramer, T Theeuwes… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A substrate having a plurality of features for use in measur ing a parameter
of a device manufacturing process and associated methods and apparatus. The …
of a device manufacturing process and associated methods and apparatus. The …