Comparison of a 65 nm CMOS Ring-and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity
J Prinzie, J Christiansen, P Moreira… - … on Nuclear Science, 2016 - ieeexplore.ieee.org
In this work, a comparison has been made between a low noise ring-oscillator and an LC-
oscillator Phase Locked Loop (PLL). An ASIC has been developed to conduct irradiation …
oscillator Phase Locked Loop (PLL). An ASIC has been developed to conduct irradiation …
5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays
A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA
(Field Programmable Gate Array) is sensitive to nonlinearities because of significant …
(Field Programmable Gate Array) is sensitive to nonlinearities because of significant …
A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS
This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock
generation in harsh environments like nuclear and space applications. The PLL has been …
generation in harsh environments like nuclear and space applications. The PLL has been …
A SPAD-based random number generator pixel based on the arrival time of photons
A quantum random generator based on photon detection is here presented. The system
consists of a photon source, typically a commercial LED, coupled with a detector with single …
consists of a photon source, typically a commercial LED, coupled with a detector with single …
Tradeoffs in time-to-digital converter architectures for harsh radiation environments
Performance degradation of standard time-to-digital converters (TDCs) is inevitable due to
the effects of ionizing radiation. In this article, the tradeoffs of different mitigation techniques …
the effects of ionizing radiation. In this article, the tradeoffs of different mitigation techniques …
A self-calibrated bang–bang phase detector for low-offset time signal processing
This brief describes a self-calibrated bang-bang phase detector that has been implemented
in a delay-locked loop (DLL) stabilized time-to-digital converter for high-energy physics …
in a delay-locked loop (DLL) stabilized time-to-digital converter for high-energy physics …
A Sub-10ps Resolution Multichannel Time-to-Digital Converter with Two-Stage Interpolation for High-Energy Physics Applications
J Qin, J Zhao, Z Li, J Li, D Guo… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This paper presents the design of a sub-10 ps resolution 16-channel Time-to-Digital
Converter (TDC) for high-energy physics applications. The architecture is based on a coarse …
Converter (TDC) for high-energy physics applications. The architecture is based on a coarse …
A vernier caliper time-to-digital converters with ultralow nonlinearity in fpgas
Y Jiao, X Shi, L Zhou, W Chen… - 2020 IEEE 20th …, 2020 - ieeexplore.ieee.org
A vernier caliper time-to-digital converter (VC-TDC) based on field programmable gate array
(FPGA) is proposed in this paper. The VC-TDC consists of a central carry chain and (N-1) …
(FPGA) is proposed in this paper. The VC-TDC consists of a central carry chain and (N-1) …
Delay line design for high-resolution time-to-digital converters
O Khoruzhenko - 2024 - jyx.jyu.fi
Microelectronic technology is constantly scaling towards more modern, advanced, smaller
technology nodes, which allows higher operational speeds and more robustness to total …
technology nodes, which allows higher operational speeds and more robustness to total …
A low noise clock generator for high-resolution time-to-digital convertors
J Prinzie, J Christiaensen, P Moreira… - Journal of …, 2016 - iopscience.iop.org
A robust PLL clock generator has been designed for the harsh environment in high-energy
physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 …
physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 …