The expanding gap between microprocessor and DRAM performance has necessitated the
use of increasingly aggressive techniques designed to reduce or hide the latency of main …

Remote memory techniques for datacenter applications have recently gained a great deal of
popularity. Existing remote memory techniques focus on the efficiency of a single application …

Data Access and Storage Management for Embedded Programmable Processors gives an
overview of the state-of-the-art in system-level data access and storage management for …

Containers offer an efficient way to run workloads as independent microservices that can be
developed, tested and deployed in an agile manner. To facilitate this process, container …

Machine learning algorithms have shown potential to improve prefetching performance by
accurately predicting future memory accesses. Existing approaches are based on the …

Caches are widely used in modern computer systems to bridge the increasing gap between
processor speed and memory access time. On the other hand, presence of caches …

Graphics Processing Units (GPUs) utilize memory hierarchy and Thread-Level Parallelism
(TLP) to tolerate off-chip memory latency, which is a significant bottleneck for memory-bound …

Data prefetching hides memory latency by predicting and loading necessary data into cache
beforehand. Most prefetchers in the literature are efficient for specific memory address …

The rapid development of Big Data coupled with slowing down of Moore's law has made the
memory performance a bottleneck in the von Neumann architecture. Machine learning has …

Memory system performance is a major bottleneck in large-scale graph analytics. Data
prefetching can hide memory latency; this relies on accurate prediction of memory accesses …