Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis
R Ghosh, RP Nelapati - Silicon, 2024 - Springer
This article presents the reliability analysis of a High-k stacked Dual Gate Junction-less
MOSFET at Deep Cryogenic Temperatures (as low as 50 Kelvin) in terms of dc, analog and …
MOSFET at Deep Cryogenic Temperatures (as low as 50 Kelvin) in terms of dc, analog and …
Investigation of Analog/RF behaviour of Asymmetrical Gate Tunnel FET at Cryogenic temperatures
This paper extensively sheds light on the performance of an Asymmetrical-gate Tunnel FET
(A-TFET) under cryogenic temperatures (< 78 K) in terms of DC, Analog, and RF metrics …
(A-TFET) under cryogenic temperatures (< 78 K) in terms of DC, Analog, and RF metrics …