Dynamically managing the communication-parallelism trade-off in future clustered processors

R Balasubramonian, S Dwarkadas… - Proceedings of the 30th …, 2003 - dl.acm.org
Clustered microarchitectures are an attractive alternative to large monolithic superscalar
designs due to their potential for higher clock rates in the face of increasingly wire-delay …

Trends toward on-chip networked microsystems

TM Pinkston, J Shin - International Journal of High …, 2005 - inderscienceonline.com
This survey paper identifies some trends in the application, implementation technology, and
processor architecture areas. A taxonomy which captures the influence of these trends on …

Tracing object-oriented code into functional requirements

G Antoniol, G Canfora, G Casazza… - … iwpc 2000. 8th …, 2000 - ieeexplore.ieee.org
Software system documentation is almost always expressed informally, in natural language
and free text. Examples include requirement specifications, design documents, manual …

Dynamic strands: Collapsing speculative dependence chains for reducing pipeline communication

PG Sassone, DS Wills - 37th International Symposium on …, 2004 - ieeexplore.ieee.org
In the modern era of wire-dominated architectures, specific effort must be made to reduce
needless communication within out-of-order pipelines while still maintaining binary …

Distributing the frontend for temperature reduction

P Chaparro, G Magklis, J González… - … Symposium on High …, 2005 - ieeexplore.ieee.org
Due to increasing power densities, both on-chip average and peak temperatures are fast
becoming a serious bottleneck in processor design. This is due to the cost of removing the …

Thermal-aware clustered microarchitectures

P Chaparro, J Gonzalez… - … Conference on Computer …, 2004 - ieeexplore.ieee.org
As frequencies and feature size scale faster than operating voltages, power density is
increasing in each processor generation. Power density and the cost of removing the heat it …

On characterizing performance of the cell broadband engine element interconnect bus

TW Ainsworth, TM Pinkston - … on Networks-on-Chip (NOCS'07), 2007 - ieeexplore.ieee.org
With the rise of multicore computing, the design of on-chip networks (or networks on chip)
has become an increasingly important component of computer architecture. The cell …

Microarchitectural wire management for performance and power in partitioned architectures

R Balasubramonian, N Muralimanohar… - … Symposium on High …, 2005 - ieeexplore.ieee.org
Future high-performance billion-transistor processors are likely to employ partitioned
architectures to achieve high clock speeds, high parallelism, low design complexity, and low …

[PDF][PDF] Thermal-effective clustered microarchitectures

P Chaparro, J González, A González - power, 2004 - academia.edu
As frequencies and feature size scale faster than operating voltages, power density is
increasing in every processor generation. Along with that, leakage (highly dependent on …

Hardware-modulated parallelism in chip multiprocessors

J Chen, P Juang, K Ko, G Contreras, D Penry… - ACM SIGARCH …, 2005 - dl.acm.org
Chip multi-processors (CMPs) already have widespread commercial availability, and
technology roadmaps project enough on-chip transistors to replicate tens or hundreds of …