In‐memory computing with memristor content addressable memories for pattern matching
The dramatic rise of data‐intensive workloads has revived application‐specific
computational hardware for continuing speed and power improvements, frequently achieved …
computational hardware for continuing speed and power improvements, frequently achieved …
[图书][B] Parallel computation: models and methods
SG Akl - 1997 - dl.acm.org
Parallel computation | Guide books skip to main content ACM Digital Library home ACM home
Google, Inc. (search) Advanced Search Browse About Sign in Register Advanced Search …
Google, Inc. (search) Advanced Search Browse About Sign in Register Advanced Search …
Ac-dimm: associative computing with stt-mram
With technology scaling, on-chip power dissipation and off-chip memory bandwidth have
become significant performance bottlenecks in virtually all computer systems, from mobile …
become significant performance bottlenecks in virtually all computer systems, from mobile …
Hyper-AP: Enhancing associative processing through a full-stack optimization
Associative processing (AP) is a promising PIM paradigm that overcomes the von Neumann
bottleneck (memory wall) by virtue of a radically different execution model. By decomposing …
bottleneck (memory wall) by virtue of a radically different execution model. By decomposing …
GP-SIMD processing-in-memory
GP-SIMD, a novel hybrid general-purpose SIMD computer architecture, resolves the issue of
data synchronization by in-memory computing through combining data storage and …
data synchronization by in-memory computing through combining data storage and …
Computer architecture with associative processor replacing last-level cache and SIMD accelerator
This study presents a computer architecture, where a last-level cache and a SIMD
accelerator are replaced by an associative processor. Associative processor combines data …
accelerator are replaced by an associative processor. Associative processor combines data …
CAPE: A content-addressable processing engine
Processing-in-memory (PIM) architectures attempt to overcome the von Neumann bottleneck
by combining computation and storage logic into a single component. The content …
by combining computation and storage logic into a single component. The content …
A simple implementation of Dijkstra's shortest path algorithm on associative parallel processors
AS Nepomniaschaya… - Fundamenta Informaticae, 2000 - content.iospress.com
In this paper we propose a natural straight forward implementation of Dijkstra's shortest path
algorithm on a model of associative parallel processors of the SIMD type with bit-serial (or …
algorithm on a model of associative parallel processors of the SIMD type with bit-serial (or …
Design for strong testability of RTL data paths to provide complete fault efficiency
H Wada, T Masuzawa, KK Saluja… - VLSI Design 2000 …, 2000 - ieeexplore.ieee.org
In this paper, we propose a DFT method for RTL data paths to achieve 100% fault efficiency.
The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The …
The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The …
Method for recognizing and interpreting patterns in noisy data sequences
JL Potter - US Patent 8,504,374, 2013 - Google Patents
US8504374B2 - Method for recognizing and interpreting patterns in noisy data sequences -
Google Patents US8504374B2 - Method for recognizing and interpreting patterns in noisy data …
Google Patents US8504374B2 - Method for recognizing and interpreting patterns in noisy data …