When the international technology roadmap of semiconductors (ITRS) started almost five
decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) …

The Cu/low-k damascene process was introduced to alleviate the increase in the RC delay
of Al/SiO2 interconnects, but now that the technology generation has reached 1× nm or …

In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet
field-effect transistors are compared for the 5​ nm technology node. The performance of …

Electromigration and resistivity of Cu, Co and Ru on-chip interconnections have been
investigated. Non-linered Co and Ru interconnects can have better interconnect resistance …

Cryogenic computing can achieve high performance and power efficiency by dramatically
reducing the device's leakage power and wire resistance at low temperatures. Recent …

Area-selective depositions (ASDs) exploit surface reactivity differences to deposit a material
on a desired growth surface. This chemically driven process produces a reflection of the …

We apply first-principles simulations to evaluate several properties related to the resistance
and reliability of rhodium and iridium interconnects. We find that both Rh and Ir have …

To predict the impact of technological variables such as materials, dimensions, interfaces,
and operating conditions on Cu electromigration, in this study a hybrid modeling framework …

Integrated circuits are presently constructed using top-down strategies composed of multiple
etching and lithographic steps. As the feature sizes of these devices approach single-digit …

In this study, we demonstrate a quasi van der Waals epitaxy approach to prepare an
epitaxial Ru ultrathin film on large-scale, single-crystalline, monolayer graphene. Physical …