The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …

To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Fine-grained dynamic voltage/frequency scaling (DVFS) demonstrates great promise for
improving the energy-efficiency of chip-multiprocessors (CMPs), which have emerged as a …

An asynchronous pipeline style is introduced for high-speed applications, called
MOUSETRAP. The pipeline uses standard transparent latches and static logic in its …

Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully
synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD …

Due to shrinking technologies and increasing design sizes, it is becoming more difficult and
expensive to distribute a global clock signal with low skew throughout a processor die …

Today's networks of processors on and off chip, operating with independent clocks, need
effective synchronization of the data passing between them for reliability. When two or more …

With increasing integration densities, large chip designs are commonly partitioned into
multiple clock domains. While the computation within each individual domain may be …

Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing
the balance between power and performance in chip-multiprocessors. Although …

This paper presents several low-latency mixed-timing FIFO (first-in-first-out) interfaces
designs that interface systems on a chip working at different speeds. The connected systems …