Chaotic encryption for 10-Gb Ethernet optical links

A Pérez-Resa, M Garcia-Bosque… - … on Circuits and …, 2018 - ieeexplore.ieee.org
In this paper, a new physical layer encryption method for optical 10-Gb Ethernet links is
proposed. Necessary modifications to introduce encryption in Ethernet 10GBase-R standard …

Analysis of a multiwire, multilevel, and symbol correlation combination scheme

J Choi, Y Choi, H Park, J Sim, Y Kwon… - … on Circuits and …, 2022 - ieeexplore.ieee.org
The required data rate of wireline communications has increased; however, channel
attenuation limits the data bandwidth. Bit-efficient signaling is an effective and efficient …

Basic study of both-sides retrodirective system for minimizing the leak energy in microwave power transmission

T Matsumuro, Y Ishikawa… - IEICE Transactions on …, 2019 - search.ieice.org
In the beam-type microwave power transmission system, it is required to minimize the
interference with communication and the influence on the human body. Retrodirective …

A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques

J Sim, J Choi, Y Kwon, S Park, S Kim… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
This article presents a wireline transceiver using 3-bit per symbol signaling techniques that
can simultaneously modulate and demodulate the common-mode (CM) 1-bit non-return to …

A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme

W Xiao, Q Huang, H Mosalam, C Zhan… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper presents a low power injection-locked oscillator (ILO)-type clock and data
recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to …

A flexible 0.73–15.5 GHz single LC VCO clock generator in 12 nm CMOS

H Xu, B Luo, G Jin, F Feng, H Guo… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This brief presents a compact and flexible 0.73–15.5 GHz clock generator with only a single
LC-VCO. A 50% duty cycle divide-by-1.5 divider (Div-1.5) is employed to reduce the …

A software PAM4 clock data recovery algorithm for high‐speed serial communication

T Wu, K Song, Z Chen, H Zhao, H Yu - IET communications, 2022 - Wiley Online Library
Time jitter analysis is an important means to evaluate the performance of a high‐speed
serial communication system. Clock data recovery (CDR) is a critical component of a high …

A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD

CC Wang, LSSPK Chodisetti, BH Liao, P Vellanki… - Microelectronics …, 2024 - Elsevier
A dual-loop CDR (Clock and Data Recovery) is presented to recover digital data from 1 to
6.5 Gbps. The presented frequency acquisition technique is based on full rate clock …

A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR

W Chen, Q Cai, Z Yang, S Qiao - IEICE Electronics Express, 2023 - jstage.jst.go.jp
In this work, a high-speed four-channel 0.8–6Gb/s wireline receiver was reported. Based on
spectrum-balancing (SB) equalizer and slicer amplitude attenuator, it can be automatically …

A jitter-tolerant referenceless digital-CDR for cellular transceivers

J Kim, Y Ko, J Jin, J Choi… - 2020 IEEE Asian Solid …, 2020 - ieeexplore.ieee.org
A half-rate jitter-tolerant referenceless digital clock and data recovery (D-CDR) circuit for
cellular transceivers is presented. For a referenceless configuration, we introduced a half …