Stacked nanosheet field-effect transistor with air gap spacers
J Frougier, R Xie, H Zang, K Cheng… - US Patent …, 2019 - Google Patents
Structures for a nanosheet field-effect transistor and methods for forming a structure for a
nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer …
nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer …
Semiconductor device
DW Kim, HJ Lee, S Kim, SH Lee, K Park… - US Patent …, 2018 - Google Patents
8, 987, 794 B23/2015 Rachmady et al. 8, 994, 081 B23/2015 Leobandung 2014/0001441
AL 1/2014 Kim et al. 2014/0225169 Al 8/2014 Suk et al. 2015/0079751 A1 3/2015 Alptekin …
AL 1/2014 Kim et al. 2014/0225169 Al 8/2014 Suk et al. 2015/0079751 A1 3/2015 Alptekin …
Semiconductor device and manufacturing method thereof
WY Lee, FC Yang, TY Chen - US Patent 9,865,504, 2018 - Google Patents
ABSTRACT A semiconductor device includes an isolation layer disposed over a substrate,
first and second fin structures, a gate structure, a source/drain structure and a dielectric layer …
first and second fin structures, a gate structure, a source/drain structure and a dielectric layer …
Semiconductor structure with recessed source/drain structure and method for forming the same
KC Ching, CW Tsai, YK Leung - US Patent 9,922,978, 2018 - Google Patents
(57) ABSTRACT A semiconductor structure and a method for forming the same are provided.
The semiconductor structure includes a fin structure formed over a substrate and a first gate …
The semiconductor structure includes a fin structure formed over a substrate and a first gate …
Semiconductor device and manufacturing method thereof
KH Fung - US Patent 9,755,019, 2017 - Google Patents
(57) ABSTRACT A semiconductor device includes an isolation layer, first and second fin
structures, a gate structure and a source/drain structure. The isolation layer is disposed over …
structures, a gate structure and a source/drain structure. The isolation layer is disposed over …
Substrates and transistors with 2D material channels on 3D geometries
V Moroz, J Huang, J Kawa - US Patent 10,411,135, 2019 - Google Patents
Roughly described, a transistor is formed with a semicon ductor 2D material layer wrapped
conformally on at least part of a 3D structure. The 3D structure can be for example a ridge …
conformally on at least part of a 3D structure. The 3D structure can be for example a ridge …
Semiconductor device blocking leakage current and method of forming the same
HK Yu, K Kim, C Park, DS Shin, Y Lim… - US Patent 9,865,698, 2018 - Google Patents
2016-02-25 Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG
ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
Method for forming merged contact for semiconductor device
E Alptekin, B Pranatharthiharan… - US Patent …, 2016 - Google Patents
(57) ABSTRACT A method for forming a semiconductor device comprises forming a first fin
and a second fin on a semiconductor Substrate, forming a sacrificial gate stack over a …
and a second fin on a semiconductor Substrate, forming a sacrificial gate stack over a …
Vertical transistors with improved top source/drain junctions
K Cheng, M Sankarapandian, R Xie… - US Patent …, 2019 - Google Patents
A method of fabricating a top source/drain junction of a vertical transistor includes forming a
structure including a bottom source/drain, a fin channel extending vertically from the bottom …
structure including a bottom source/drain, a fin channel extending vertically from the bottom …
Semiconductor device and manufacturing method thereof
KH Fung - US Patent 10,141,307, 2018 - Google Patents
(57) ABSTRACT A semiconductor device includes an isolation layer, first and second fin
structures, a gate structure and a source/drain structure. The isolation layer is disposed over …
structures, a gate structure and a source/drain structure. The isolation layer is disposed over …