An on/off keying receiver has been designed in 90 nm CMOS for low-power event-driven
applications. Thanks to the synchronized-switching technique and power-efficient RF gain …

A 2.4 GHz PLL consuming 0.68 mW has been implemented in 65nm LPCMOS for use in
ultra-low power Bluetooth Low Energy (BLE) applications. VCO, charge pump and dynamic …

This paper presents a sub-mW single supply fractional-NPLL for Narrowband IoT (NB-IoT)
applications. The analog PLL meets the relatively strict spur requirement of NB-IoT while …

This article presents a low supply voltage and low-power charge-pump phase-locked loop
(CPPLL) with phase noise (PN) improvement and reference spur reduction techniques. The …

In most phase locked loops, an obvious trade-off exists between settling time, output jitter
and power consumption. However, dependence of jitter on settling time is commonly …

This article presents a fractional-N phase-locked loop (PLL) for the use in frequency-
modulated continuous wave (FMCW) radar systems. The presented design supports division …

A 1 V low voltage, low power integer-N frequency synthesizer applied for 2.4 GHz wireless
sensor network (WSN) applications is presented. The loop parameters of proposed charge …

Compressive sensing has been demonstrated as an appealing technique in the
implementation of low-power sensors. This work studies the feasibility and potential power …

This work presents a robust dual band local positioning system (LPS) working in the 2. 4GHz
and 5. 8GHz industrial science medical (ISM) bands. Position measurement is based on the …

This paper presents an ultra-low power alldigital phase-locked loop (ADPLL) with 543 fs rms
jitter. Fabricated in a commercial 28-nm CMOS technology, the ADPLL covers 3.95-to-4.685 …