Arbitrating among portions of multiple transactions and transmitting a winning portion over
one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by …

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as
expanding transactions and consolidating responses at nodes of an interconnect fabric for …

A system for consistently implementing reset and power management of IP agents on a
System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes …

Arbitrating among portions of multiple transactions and transmitting a winning portion over
one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by …

Optimizing transaction trafic on a System on a Chip (SoC) by using procedures such as
expanding transactions and consolidating responses at nodes of an interconnect fabric for …

A data processing apparatus includes a master device configured to transmit commands for
destinations, a slave device including a plurality of command processing regions …

Arbitration circuitry is provided to select an output from between multiple inputs each having
an associated priority value. A tie-break value is appended to the least significant bits of …

A system for consistently implementing reset and power management of IP agents on a
System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes …

An interconnect within an integrated circuit provides arbitration to select one of a plurality of
signal inputs for connection to a signal output. The arbitration applied uses a first arbitration …