A heterogeneous digital signal processor for dynamically reconfigurable computing
This paper describes a System on Chip implementation of a reconfigurable digital signal
processor. The device is suitable for execution of a wide range of applications exploiting a …
processor. The device is suitable for execution of a wide range of applications exploiting a …
Networked dual-mode adaptive horizon MPC for constrained nonlinear systems
This article investigates the predictive control scheme and related stability issue for a class
of discrete-time perturbed nonlinear system with state and input constraints. First, we …
of discrete-time perturbed nonlinear system with state and input constraints. First, we …
A fully programmable eFPGA-augmented SoC for smart power applications
F Renzini, C Mucci, D Rossi… - … on Circuits and …, 2019 - ieeexplore.ieee.org
This paper proposes a reconfigurable system on chip (SoC) for smart power applications.
The system is composed of an ultra-low-power microcontroller for standard software …
The system is composed of an ultra-low-power microcontroller for standard software …
Application space exploration of a heterogeneous run-time configurable digital signal processor
This paper describes the application space exploration of a heterogeneous digital signal
processor with dynamic reconfiguration capabilities. The device is built around three …
processor with dynamic reconfiguration capabilities. The device is built around three …
[PDF][PDF] Logical-mathematical model of encoder 2D-RS for hardware description in VHDL
CE Sandoval-Ruiz - Rev. Ing. UC, 2017 - servicio.bc.uc.edu.ve
In this research, a logical-mathematical model of the Reed Solomon encoder is developed
in two-dimensions, based on the optimized model of the LFSR components (linear feedback …
in two-dimensions, based on the optimized model of the LFSR components (linear feedback …
[HTML][HTML] VHDL optimized model of a multiplier in finite fields
C Sandoval-Ruiz - Ingeniería y universidad, 2017 - scielo.org.co
Abstract SANDOVAL-RUIZ, Cecilia. VHDL Optimized Model of a Multiplier in Finite Fields.
Ing. Univ.[online]. 2017, vol. 21, n. 2, pp. 195-211. ISSN 0123-2126. https://doi …
Ing. Univ.[online]. 2017, vol. 21, n. 2, pp. 195-211. ISSN 0123-2126. https://doi …
多输出LFSR 结构均匀分布伪随机数生成器的硬件设计优化
谷晓忱， 张民选 - 武汉大学学报(信息科学版), 2010 - ch.whu.edu.cn
通过公式推导, 得出了使用硬件方式实现伪随机数生成器所消耗的硬件资源数量与输出位数和所
产生随机数周期之间的关系, 从理论层面上证明了多输出LFSR 结构在硬件资源利用方面存在的 …
产生随机数周期之间的关系, 从理论层面上证明了多输出LFSR 结构在硬件资源利用方面存在的 …
A study of adaptable co-processors for cyclic redundancy check on an fpga
Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect
corruption of digital content in digital networks and storage devices. In this paper, we present …
corruption of digital content in digital networks and storage devices. In this paper, we present …
An Efficient Multi‐Core SIMD Implementation for H. 264/AVC Encoder
M Bariani, P Lambruschini, M Raggio - VLSI Design, 2012 - Wiley Online Library
The optimization process of a H. 264/AVC encoder on three different architectures is
presented. The architectures are multi‐and singlecore and SIMD instruction sets have …
presented. The architectures are multi‐and singlecore and SIMD instruction sets have …
Deep representation-based packetized predictive compensation for networked nonlinear systems
S Chen, Y Cao, Y Kang, B Sun, X Wang - Neural Computing and …, 2021 - Springer
The design of networked nonlinear control system is a very challenging problem due to the
coupling of the system uncertainties (eg, model accuracy, noise, nonlinearity) and network …
coupling of the system uncertainties (eg, model accuracy, noise, nonlinearity) and network …