We present in this paper a new algorithm for floorplan design using the method of simulated
annealing. The major contributions of the paper are: 1. A new representation of floorplans …

This thesis develops a theoretical model for the wiring complexity of wide classes of
systems, relating the degree of connectivity of a circuit to the dimensionality of its …

The current status of VLSI layout and directions for future research are addressed, with
emphasis on the authors' own work. Necessary terminology and definitions and, whenever …

Let one face of a cube be dissected into rectangles, no 4 of which meet at a single point. The
dual graph of this configuration is a 4‐connected triangulated plane graph. This paper …

In this paper we extend the concept of the regular edge labeling for general plane graphs
and for triconnected triangulated plane graphs to 4-connected triangulated plane graphs …

Computer Aids for VLSI Design Page 1 Computer Aids for VLSI Design Steven M. Rubin
Copyright © 1994 Page 2 Appendix B: Caltech Intermediate Format Caltech Intermediate Format …

A LINEAR ALGORITHM TO FIND A RECTANGULAR DUAL OF A PLANAR TRIANGULATED
GRAPH * Jayaram Bhasker+and Sartaj Sahni University of Mi Page 1 A LINEAR ALGORITHM …

An analytical method for general floorplan design and optimization is proposed. This method
is based on a mixed integer programming model and application of a standard mathematical …

This paper presents a new linear-time algorithm for finding rectangular duals of planar
triangular graphs. The algorithm is conceptually simpler than the previously known …

A new methodology for hierarchical floor planning and global routing for building block
layout is presented. Unlike the traditional approach, which separates placement and global …