This book aims at describing in detail the different layout techniques for remarkably boosting
the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide …

Some special effects of SOI devices with diamond layout are analyzed in this paper based
on the silicon data from 130 nm PD-SOI T-gate MOSFET. LCE and PAMDLE induced current …

We examine the impact of line-edge roughness (LER) on the variability in the on-current and
saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical …

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate
oxide thickness of short channel asymmetric double gate (DG) MOSFET. The ratio of …

In the present research work, the influence of Fin width thickness variation on the electrical
performance parameters have been performed for the 14-nm FinFET device. Various Fin …

To support the current level of integration beyond 22 nm, the FinFET architecture is
introduced with the expectation of greater levels of device matching. An additional …

We investigate the channel material dependence of wave function deformation scattering
(WDS), a phenomenon that occurs when the shape of the carrier wave function is forced to …

The electronics industry has already moved to non-conventional transistor geometries in
order to overcome the limitations associated with aggressive transistor scaling. Fin field …

The effect of the nanoscale bitline string thickness on the electrical characteristics of vertical
NAND flash memory devices was investigated. The trapped charge magnitude in the nitride …

요 약본 논문에서는 단채널 비대칭 이중게이트 MOSFET 의 상하단 산화막 두께비에 대한
터널링 전류의 변화에 대하여 분석하고자 한다. 채널길이가 5 nm 까지 감소하면 차단전류에서 …