Disturbance aware dynamic power reduction in synchronous 2RW dual-port 8T SRAM by self-adjusting wordline pulse timing
Y Yokoyama, K Nii, Y Ishii, S Tanaka… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
An effective design is proposed to reduce dynamic power consumption for a common clock
synchronous two-read/write (2RW) dual-port (DP) 8T static random access memory (SRAM) …
synchronous two-read/write (2RW) dual-port (DP) 8T static random access memory (SRAM) …
Aging Effects On Clock Gated Memory Phase Paths
Transistor aging is a critical reliability issue affecting all nanoscale designs in advanced
CMOS technologies. The aging affects the electrical properties of the transistors over time …
CMOS technologies. The aging affects the electrical properties of the transistors over time …
Augmented Memory Computing: Dynamically Augmented SRAM Storage for Data Intensive Applications
H Sheshadri, S Vijayakumar, A Jacob… - arXiv preprint arXiv …, 2021 - arxiv.org
In this paper, we propose a novel memory-centric scheme based on CMOS SRAM for
acceleration of data intensive applications. Our proposal aims at dynamically increasing the …
acceleration of data intensive applications. Our proposal aims at dynamically increasing the …
Fast, Energy Efficient CMOS 2P1R1W Register File Array using Harvested Data
A Bhavnagarwala - US Patent App. 17/578,482, 2023 - Google Patents
US20230120936A1 - Fast, Energy Efficient CMOS 2P1R1W Register File Array using
Harvested Data - Google Patents US20230120936A1 - Fast, Energy Efficient CMOS …
Harvested Data - Google Patents US20230120936A1 - Fast, Energy Efficient CMOS …
Augmented memory computing: a new pathway for efficient ai computations
US20240282366A1 - Augmented memory computing: a new pathway for efficient ai
computations - Google Patents US20240282366A1 - Augmented memory computing: a …
computations - Google Patents US20240282366A1 - Augmented memory computing: a …