Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation
Two major trends in high-performance computing, namely, larger numbers of cores and the
growing size of on-chip cache memory, are creating significant challenges for evaluating the …
growing size of on-chip cache memory, are creating significant challenges for evaluating the …
An evaluation of high-level mechanistic core models
Large core counts and complex cache hierarchies are increasing the burden placed on
commonly used simulation and modeling techniques. Although analytical models provide …
commonly used simulation and modeling techniques. Although analytical models provide …
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (eg, in-
order) power-efficient cores and big (eg, out-of-order) high-performance cores. The …
order) power-efficient cores and big (eg, out-of-order) high-performance cores. The …
GPGPU performance and power estimation using machine learning
G Wu, JL Greathouse, A Lyashevsky… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Graphics Processing Units (GPUs) have numerous configuration and design options,
including core frequency, number of parallel compute units (CUs), and available memory …
including core frequency, number of parallel compute units (CUs), and available memory …
MISE: Providing performance predictability and improving fairness in shared main memory systems
Applications running concurrently on a multicore system interfere with each other at the main
memory. This interference can slow down different applications differently. Accurately …
memory. This interference can slow down different applications differently. Accurately …
Power-performance modeling on asymmetric multi-cores
M Pricopi, TS Muthukaruppan… - … and Synthesis for …, 2013 - ieeexplore.ieee.org
Asymmetric multi-core architectures have recently emerged as a promising alternative in a
power and thermal constrained environment. They typically integrate cores with different …
power and thermal constrained environment. They typically integrate cores with different …
Green governors: A framework for continuously adaptive dvfs
V Spiliopoulos, S Kaxiras… - 2011 International Green …, 2011 - ieeexplore.ieee.org
We present Continuously Adaptive Dynamic Voltage/Frequency scaling in Linux systems
running on Intel i7 and AMD Phenom II processors. By exploiting slack, inherent in memory …
running on Intel i7 and AMD Phenom II processors. By exploiting slack, inherent in memory …
Interval simulation: Raising the level of abstraction in architectural simulation
D Genbrugge, S Eyerman… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
Detailed architectural simulators suffer from a long development cycle and extremely long
evaluation times. This longstanding problem is further exacerbated in the multi-core …
evaluation times. This longstanding problem is further exacerbated in the multi-core …
ArchExplorer: Microarchitecture exploration via bottleneck analysis
Design space exploration (DSE) for microarchitecture parameters is an essential stage in
microprocessor design to explore the trade-offs among performance, power, and area …
microprocessor design to explore the trade-offs among performance, power, and area …
Fine-grained DVFS using on-chip regulators
S Eyerman, L Eeckhout - ACM Transactions on Architecture and Code …, 2011 - dl.acm.org
Limit studies on Dynamic Voltage and Frequency Scaling (DVFS) provide apparently
contradictory conclusions. On the one hand early limit studies report that DVFS is effective at …
contradictory conclusions. On the one hand early limit studies report that DVFS is effective at …