Emerging reconfigurable electronic devices based on two‐dimensional materials: A review
As the dimensions of the transistor, the key element of silicon technology, are approaching
their physical limits, developing semiconductor technology with novel concepts and …
their physical limits, developing semiconductor technology with novel concepts and …
Progress in Contact, Doping and Mobility Engineering of MoS2: An Atomically Thin 2D Semiconductor
Atomically thin molybdenum disulfide (MoS2), a member of the transition metal
dichalcogenide (TMDC) family, has emerged as the prototypical two-dimensional (2D) …
dichalcogenide (TMDC) family, has emerged as the prototypical two-dimensional (2D) …
Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman… - … on Electron Devices, 2017 - ieeexplore.ieee.org
In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from
intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and …
intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and …
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
A Veloso, T Huynh-Bao, P Matagne, D Jang… - Solid-State …, 2020 - Elsevier
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
A 10 nm FinFET 128 Mb SRAM with assist adjustment system for power, performance, and area optimization
Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
6T SRAM bitcell is designed for high density (HD), and 0.049 for high performance (HP). The …
Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
V Vashishtha, LT Clark - Microelectronics Journal, 2021 - Elsevier
In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet
field-effect transistors are compared for the 5 nm technology node. The performance of …
field-effect transistors are compared for the 5 nm technology node. The performance of …
Optimization of structure and electrical characteristics for four-layer vertically-stacked horizontal gate-all-around Si nanosheets devices
Q Zhang, J Gu, R Xu, L Cao, J Li, Z Wu, G Wang, J Yao… - Nanomaterials, 2021 - mdpi.com
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si
nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release …
nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release …
Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG
Development of an industry leading 10nm CMOS process technology with the highest
reported drive currents and cell densities involved numerous enabling innovations, judicious …
reported drive currents and cell densities involved numerous enabling innovations, judicious …
Neuromorphic vision hybrid RRAM-CMOS architecture
JK Eshraghian, K Cho, C Zheng, M Nam… - … Transactions on Very …, 2018 - ieeexplore.ieee.org
The development of a bioinspired image sensor, which can match the functionality of the
vertebrate retina, has provided new opportunities for vision systems and processing through …
vertebrate retina, has provided new opportunities for vision systems and processing through …
Design insights into thermal performance of vertically stacked JL-NSFET with high-k gate dielectric for sub 5-nm technology node
Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate
Dielectric for Sub 5-nm Technology Node - IOPscience Skip to content IOP Science home …
Dielectric for Sub 5-nm Technology Node - IOPscience Skip to content IOP Science home …