Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

Transmeta's Crusoe microprocessor is a full, system-level implementation of the x86
architecture, comprising a native VLIW microprocessor with a software layer, the Code …

IA-32 execution layer (IA-32 EL) is a new technology that executes IA-32 applications on
Intel Itanium processor family systems. Currently, support for IA-32 applications on Itanium …

We describe a VLIW architecture designed specifically as a target for dynamic compilation of
an existing instruction set architecture. This design approach offers the simplicity and high …

Conventional out-of-order processors employ a multi-ported, fully-associative load queue to
guarantee correctmemory reference order both within a single thread of executionand …

Virtualization is emerging as an important technology in future systems, providing an extra
layer of abstraction between the hardware and operating system. Previous work on …

6,009.261 6,094,695 6,185,629 6,189,088 6, 192466 6,308,255 6,334, 176 6,338,057
6,349,361 6,381,691 6,408,383 6,449,706 6.463, 582 6,499,116 6,513,109 6,570,511 …

Processing of character data is facilitated. A Vector String Range Compare instruction is
provided that compares each element of a vector with a range of values based on a set of …

Processing of character data is facilitated. A Find Element Not Equal instruction is provided
that compares data of multiple vectors for inequality and provides an indication of inequality …

The end of Dennard Scaling has forced architects to focus on designing for execution
efficiency. Course-grained reconfigurable architectures (CGRAs) are a class of architectures …