Content-addressable memory (CAM) circuits and architectures: A tutorial and survey
K Pagiamtzis, A Sheikholeslami - IEEE journal of solid-state …, 2006 - ieeexplore.ieee.org
We survey recent developments in the design of large-capacity content-addressable
memory (CAM). A CAM is a memory that implements the lookup-table function in a single …
memory (CAM). A CAM is a memory that implements the lookup-table function in a single …
Digital circuit design challenges and opportunities in the era of nanoscale CMOS
Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
[图书][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
OpenRAM: An open-source memory compiler
Computer systems research is often inhibited by the availability of memory designs. Existing
Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial …
Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial …
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications
K Takeda, Y Hagihara, Y Aimoto… - IEEE journal of solid …, 2005 - ieeexplore.ieee.org
To help overcome limits to the speed of conventional SRAMs, we have developed a read-
static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low …
static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low …
[图书][B] CMOS SRAM circuit design and parametric test in nano-scaled technologies: process-aware SRAM design and test
As technology scales into nano-meter region, design and test of Static Random Access
Memories (SRAMs) becomes a highly complex task. Process disturbances and various …
Memories (SRAMs) becomes a highly complex task. Process disturbances and various …
[图书][B] VLSI memory chip design
K Itoh - 2013 - books.google.com
The VLSI memory era truly began when the first production of semiconduc tor memory was
announced by IBM and Intel in 1970. The announcement had a profound impact on my …
announced by IBM and Intel in 1970. The announcement had a profound impact on my …
[图书][B] The VLSI handbook
WK Chen - 1999 - taylorfrancis.com
Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
Low-leakage asymmetric-cell SRAM
N Azizi, A Moshovos, FN Najm - … of the 2002 international symposium on …, 2002 - dl.acm.org
We introduce a novel family of asymmetric dual-Vt SRAM cell designs that reduce leakage
power in caches while maintaining low access latency. Our designs exploit the strong bias …
power in caches while maintaining low access latency. Our designs exploit the strong bias …
Speed and Power Scaling of SRAM's
BS Amrutur, MA Horowitz - IEEE journal of solid-state circuits, 2000 - ieeexplore.ieee.org
Simple models for the delay, power, and area of a static random access memory (SRAM) are
used to determine the optimal organizations for an SRAM and study the scaling of their …
used to determine the optimal organizations for an SRAM and study the scaling of their …