Low latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection

X He, Y Bai, Y Liu, L Du, Z Wang… - IEEE Internet of Things …, 2023 - ieeexplore.ieee.org
In Internet of Things (IoT) endpoint devices, some data or address ciphers are used for real-
time memory protection to mitigate some side-channel attacks against memories. To better …

Design of a BIST implemented AES crypto-processor ASIC

ML Ali, MS Rahman, FS Hossain - Plos one, 2021 - journals.plos.org
This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced
Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC) …

Evaluation of a modular approach to AES hardware architecture and optimization

R Swann, J Stine - Journal of Signal Processing Systems, 2023 - Springer
This paper contains an in-depth investigation into a modularized and parameterized AES
implementation with options for the addition of many different AES optimizations. This …

Efficient AES implementation on Sunway TaihuLight supercomputer: A systematic approach

L Li, J Fang, J Jiang, L Gan, W Zheng, H Fu… - Journal of Parallel and …, 2020 - Elsevier
Encryption is an important technique to improve information security for many real-world
applications. The Advanced Encryption Standard (AES) is a widely-used efficient …

A reconfigurable architecture for improvement and optimization of advanced encryption standard hardware

R Swann, JE Stine - 2021 55th Asilomar Conference on Signals …, 2021 - ieeexplore.ieee.org
This paper contains an in-depth investigation into a modularized and parameterized AES
implementation with options for addition of many different AES optimizations. This …

Design and Implementation of a Configurable Encryption System for Power-Constrained Devices

JDJ De La Rosa-De La, JS Murguía… - IEEE …, 2023 - ieeexplore.ieee.org
In this work, we present a configurable encryption system based on the Encryption by
Synchronization in a Cellular Automata (ESCA) system, which is a symmetric key algorithm …

Framework for Live Migration of FPGA based ECB-mode AES-128 accelerator

Y Asfia, SG Khawaja, M Asad… - 2022 2nd International …, 2022 - ieeexplore.ieee.org
Virtual Machines in cloud datacenters are live migrated for assuring service availability in
the event of errors and maintenance. FPGA based hardware accelerators must also be live …

A reconfigurable permutation based address encryption architecture for memory security

Y Mei, L Du, X He, Y Du, X Chen… - 2020 IEEE 33rd …, 2020 - ieeexplore.ieee.org
Most of the existing memory encryption techniques in IoT devices are based on data
encryption. The level of security increases at the cost of the increased encryption algorithm …

移动硬盘加解密板卡的设计与实现

秦宗庆, 张伯泉, 曹海波 - 微电子学与计算机, 2014 - journalmc.com
针对移动硬盘数据安全问题, 分析, 优化了AES 加密算法, 提出了Microbalze 与轮内,
轮间三级流水线AES 加解密IP 核结合的架构, 设计并实现了一种介于硬盘与电脑USB …

[PDF][PDF] Design and Implementation of a Configurable Encryption System for Power-Constrained Devices

MÁ LASTRAS-MONTAÑO - academia.edu
In this work, we present a configurable encryption system based on the Encryption by
Synchronization in a Cellular Automata (ESCA) system, which is a symmetric key algorithm …