A Type-I Sub-Sampling PLL With a Footprint and −255-dB FOM

A Sharkia, S Mirabbasi… - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
A dual-loop LC-voltage-controlled oscillator (VCO) based frequency synthesizer, composed
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …

A 0.01mm2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with −254dB FOM

A Sharkia, S Mirabbasi… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Power consumption, Performance in terms of phase noise and integrated jitter, and Area
(PPA) are three design metrics that have driven countless research efforts in CMOS …

A compact, voltage-mode type-I PLL with gain-boosted saturated PFD and synchronous peak tracking loop filter

A Sharkia, S Aniruddhan, S Mirabbasi… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Despite their inherent stability, area-efficient loop filters, and insensitivity to phase-frequency
detector nonlinearity and dead-zone, type-I phase-locked loops (PLLs) are used infrequently …

A Compact 20–24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme

L Wang, Z Liu, R Ma, CP Yue - IEEE Journal of Solid-State …, 2024 - ieeexplore.ieee.org
This article introduces a compact 20–24-GHz integer-dual-path sub-sampling phase-locked
loop (DPSSPLL) with a charge-domain bandwidth control scheme. By leveraging the …

An ultra-low power, adaptive all-digital frequency-locked loop with gain estimation and constant current DCO

I Ali, H Abbasizadeh, MRU Rehman, M Asif… - IEEE …, 2020 - ieeexplore.ieee.org
In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL)
with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth …

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector

Z Xu, A Firdauzi, M Miyahara, K Okada… - IEICE Transactions on …, 2019 - search.ieice.org
This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the
ring oscillator's noise contribution. The loop delay due to the D flip-flops at filter's output is …

A hybrid pre-loop/post-loop filtering strategy based type-1 PLL for synchronization under distorted grid conditions

H Xue, Y Cheng, M Ruan - 2019 IEEE Power & Energy Society …, 2019 - ieeexplore.ieee.org
Phase-locked loops (PLLs) are popular for the synchronization and control of grid connected
equipment and systems. The type-1 PLL is the simplest PLL, which is characterized by …